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PIC24FJ128GA010 Family Data Sheet
64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
(c) 2009 Microchip Technology Inc.
DS39747E
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS39747E-page 2
(c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU:
* Modified Harvard Architecture * Up to 16 MIPS Operation @ 32 MHz * 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options * 17-Bit x 17-Bit Single-Cycle Hardware Multiplier * 32-Bit by 16-Bit Hardware Divider * 16 x 16-Bit Working Register Array * C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes * Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Analog Features:
* 10-Bit, Up to 16-Channel Analog-to-Digital Converter - 500 ksps conversion rate - Conversion available during Sleep and Idle * Dual Analog Comparators with Programmable Input/Output Configuration
Peripheral Features:
* Two 3-Wire/4-Wire SPI modules, Supporting 4 Frame modes with 8-Level FIFO Buffer * Two I2CTM modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing * Two UART modules: - Supports RS-232, RS-485 and LIN 1.2 - On-chip hardware encoder/decoder for IrDA(R) - Auto-wake-up on Start bit - Auto-Baud Detect - 4-level FIFO buffer * Parallel Master Slave Port (PMP/PSP): - Supports 8-bit or 16-bit data - Supports 16 address lines * Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions * Programmable Cyclic Redundancy Check (CRC) - User-programmable polynomial - 8/16-level FIFO buffer * Five 16-Bit Timers/Counters with Programmable Prescaler * Five 16-Bit Capture Inputs * Five 16-Bit Compare/PWM Outputs * High-Current Sink/Source (18 mA/18 mA) on All I/O Pins * Configurable, Open-Drain Output on Digital I/O Pins * Up to 5 External Interrupt Sources * 5.5V Tolerant Input (digital pins only)
Special Microcontroller Features:
* Operating Voltage Range of 2.0V to 3.6V * Flash Program Memory: - 1000 erase/write cycles - 20-year data retention minimum * Self-Reprogrammable under Software Control * Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes * Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator * On-Chip 2.5V Regulator * JTAG Boundary Scan and Programming Support * Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation * In-Circuit Serial ProgrammingTM (ICSPTM) and In-Circuit Emulation (ICE) via 2 Pins
Compare/ PWM Output
Comparators
Device
Pins
Program Memory (Bytes) 64K 96K 128K 64K 96K 128K 64K 96K 128K
PMP/PSP Y Y Y Y Y Y Y Y Y
Capture Input
UART
SRAM (Bytes)
Timers 16-Bit
SPI
I2CTM
10-Bit A/D (ch)
PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ128GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ128GA008 PIC24FJ64GA010 PIC24FJ96GA010 PIC24FJ128GA010
64 64 64 80 80 80 100 100 100
8K 8K 8K 8K 8K 8K 8K 8K 8K
5 5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5 5
2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
16 16 16 16 16 16 16 16 16
2 2 2 2 2 2 2 2 2
(c) 2009 Microchip Technology Inc.
DS39747E-page 3
JTAG Y Y Y Y Y Y Y Y Y
PIC24FJ128GA010 FAMILY
Pin Diagrams
64-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1 PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/INT4/RD11 IC3/PMCS2/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PIC24FJXXGA006 PIC24FJXXXGA006
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/PMA13/CVREF/AN10/RB10 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
DS39747E-page 4
(c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
Pin Diagrams (Continued)
80-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T4CK/RC3 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/INT1/RE8 TDO/INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24FJXXGA008 PIC24FJXXXGA008
(c) 2009 Microchip Technology Inc.
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS U2CTS/C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 U1CTS/CN20/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
DS39747E-page 5
PIC24FJ128GA010 FAMILY
Pin Diagrams (Continued))
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PMD4/RE4 PMD3/RE3 PMD2/RE2 RG13 RG12 RG14 PMD1/RE1 PMD0/RE0 RA7 RA6 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1
RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PIC24FJXXGA010 PIC24FJXXXGA010
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 VSS VDD TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMA1/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 VSS VDD U1CTS/CN20/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DS39747E-page 6
(c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU............................................................................................................................................................................................ 21 3.0 Memory Organization ................................................................................................................................................................. 27 4.0 Flash Program Memory.............................................................................................................................................................. 47 5.0 Resets ........................................................................................................................................................................................ 53 6.0 Interrupt Controller ..................................................................................................................................................................... 59 7.0 Oscillator Configuration .............................................................................................................................................................. 93 8.0 Power-Saving Features............................................................................................................................................................ 101 9.0 I/O Ports ................................................................................................................................................................................... 103 10.0 Timer1 ...................................................................................................................................................................................... 105 11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 107 12.0 Input Capture............................................................................................................................................................................ 113 13.0 Output Compare....................................................................................................................................................................... 115 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 121 15.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 131 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 139 17.0 Parallel Master Port (PMP)....................................................................................................................................................... 147 18.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 157 19.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 169 20.0 10-bit High-Speed A/D Converter............................................................................................................................................. 173 21.0 Comparator Module.................................................................................................................................................................. 183 22.0 Comparator Voltage Reference................................................................................................................................................ 187 23.0 Special Features ...................................................................................................................................................................... 189 24.0 Instruction Set Summary .......................................................................................................................................................... 199 25.0 Development Support............................................................................................................................................................... 207 26.0 Electrical Characteristics .......................................................................................................................................................... 211 27.0 Packaging Information.............................................................................................................................................................. 225 Appendix A: Revision History............................................................................................................................................................. 231 Index ................................................................................................................................................................................................. 233 The Microchip Web Site ..................................................................................................................................................................... 237 Customer Change Notification Service .............................................................................................................................................. 237 Customer Support .............................................................................................................................................................................. 237 Reader Response .............................................................................................................................................................................. 238 Product Identification System ............................................................................................................................................................ 239
(c) 2009 Microchip Technology Inc.
DS39747E-page 7
PIC24FJ128GA010 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS39747E-page 8
(c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
1.0 DEVICE OVERVIEW
1.1.2 POWER-SAVING TECHNOLOGY
This document contains device-specific information for the following devices: * * * * * * * * * PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010 PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 All of the devices in the PIC24FJ128GA010 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. * Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. * Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software.
This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC24FJ128GA010 family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don't require the numerical processing power of a digital signal processor.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
1.1.3
OSCILLATOR OPTIONS AND FEATURES
Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC(R) digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: * 16-bit data and 24-bit address paths, with the ability to move information between data and memory spaces * Linear addressing of up to 8 Mbytes (program space) and 64 Kbytes (data) * A 16-element working register array with built-in software stack support * A 17 x 17 hardware multiplier with support for integer math * Hardware support for 32 by 16-bit division * An instruction set that supports multiple addressing modes and is optimized for high-level languages such as `C' * Operational performance up to 16 MIPS
All of the devices in the PIC24FJ128GA010 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: * Two Crystal modes using crystals or ceramic resonators. * Two External Clock modes offering the option of a divide-by-2 clock output. * A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. * A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. * A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.
(c) 2009 Microchip Technology Inc.
DS39747E-page 9
PIC24FJ128GA010 FAMILY
1.1.4 EASY MIGRATION
1.3
Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 64-pin to 80-pin to 100-pin devices. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.
Details on Individual Family Members
Devices in the PIC24FJ128GA010 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in two ways: 1. Flash program memory (64 Kbytes for PIC24FJ64GA devices, 96 Kbytes for PIC24FJ96GA devices and 128 Kbytes for PIC24FJ128GA devices). Available I/O pins and ports (53 pins on 6 ports for 64-pin devices, 69 pins on 7 ports for 80-pin devices and 84 pins on 7 ports for 100-pin devices). Note also that, since interrupt-on-change inputs are available on every I/O pin for this family of devices, the number of CN inputs also differs between package sizes.
2.
1.2
Other Special Features
* Communications: The PIC24FJ128GA010 family incorporates a range of serial communication peripherals to handle a range of application requirements. All devices are equipped with two independent UARTs with built-in IrDA encoder/decoders. There are also two independent SPI modules, and two independent I2C modules that support both Master and Slave modes of operation. * Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. * Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. * 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds.
All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ128GA010 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.
DS39747E-page 10
(c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILY
PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 128K 44,032 PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ64GA010 PIC24FJ96GA010 96K 32,768 84 100-Pin TQFP
Features
Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources (Soft Vectors/NMI Traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2CTM Parallel Communications (PMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and Delays) Instruction Set Packages 19 Ports B, C, D, E, F, G 53 64K 22,016 96K 32,768 128K 44,032 64K
DC - 32 MHz 96K 32,768 8192 43 (39/4) Ports A, B, C, D, E, F, G 69 5 2 5 5 22 Ports A, B, C, D, E, F, G 128K 44,032 64K 22,016 22,016
2 2 2 Yes Yes 16 2 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, Configuration Word Mismatch, Repeat instruction, Hardware Traps (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP 80-Pin TQFP
(c) 2009 Microchip Technology Inc.
DS39747E-page 11
PIC24FJ128GA010 FAMILY
FIGURE 1-1: PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
PORTA(1) 16 8 PSV & Table Data Access Control Block 16 16 Data Latch 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Address Latch 16 16 Read AGU Write AGU 16 PORTC RC1:RC4, RC12:RC15 PORTB(1) RB0:RB15 RA0:RA7, RA9:RA10, RA14:15
Interrupt Controller
23 Address Latch Program Memory Data Latch
Address Bus
24 Inst Latch Inst Register Instruction Decode & Control Control Signals Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference ENVREG Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) Literal Data
EA MUX 16 16
PORTD(1) RD0:RD15
PORTE(1) RE0:RE9
Divide Support 17x17 Multiplier
16 x 16 W Reg Array PORTF(1) RF0:RF8, RF12:RF13 16-Bit ALU 16 PORTG(1) RG0:RG9, RG12:RG15
OSC2/CLKO OSC1/CLKI
VDDCORE/VCAP
VDD, VSS
MCLR
Timer1
Timer2/3
Timer4/5
RTCC
10-Bit ADC
Comparators
PMP/PSP PWM/ OC1-5
IC1-5
CN1-22(1)
SPI1/2
I2C1/2
UART1/2
Note
1: 2:
Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. BOR functionality is provided when the on-board voltage regulator is enabled.
DS39747E-page 12
(c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 1-2:
Function AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS
Pin Number 64-Pin 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 19 20 35 29 12 11 21 14 13 22 39 40 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 80-Pin 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 25 26 38 35 16 15 27 18 17 28 49 50 60 59 20 19 18 17 16 15 6 7 8 10 36 66 67 68 69 39 100-Pin 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 30 31 48 39 21 20 32 23 22 33 63 64 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 I/O I I I I I I I I I I I I I I I I P P O O I I O I I O I O I I I I I I I I I I I I I I I I I I Input Buffer ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA -- -- -- -- ANA ANA -- ANA ANA -- ANA -- ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Positive Supply for Analog Modules. Ground Reference for Analog Modules. UART1 IrDA(R) Baud Clock. UART2 IrDA(R) Baud Clock. Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. Main Clock Input Connection. System Clock Output. Interrupt-on-Change Inputs. A/D Analog Inputs. Description
TTL = TTL input buffer ANA = Analog level input/output
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TABLE 1-2:
Function CN18 CN19 CN20 CN21 CVREF EMUC1 EMUD1 EMUC2 EMUD2 ENVREG IC1 IC2 IC3 IC4 IC5 INT0 INT1 INT2 INT3 INT4 MCLR OC1 OC2 OC3 OC4 OC5 OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin 32 -- -- -- 23 15 16 17 18 57 42 43 44 45 52 35 42 43 44 45 7 46 49 50 51 52 17 30 39 40 15 16 17 18 80-Pin 40 65 37 38 29 19 20 21 22 71 54 55 56 57 64 45 13 14 52 53 9 58 61 62 63 66 21 36 49 50 19 20 21 22 100-Pin 50 80 47 48 34 24 25 26 27 86 68 69 70 71 79 55 18 19 66 67 13 72 76 77 78 81 26 44 63 64 24 25 26 27 I/O I I I I O I/O I/O I/O I/O I I I I I I I I I I I I O O O O O I I I O I/O I/O I/O I/O Input Buffer ST ST ST ST ANA ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- -- -- -- -- ST ST ANA ANA ST ST ST ST Output Compare Fault A Input. Output Compare Fault B Input. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger and ICSPTM Programming Clock. In-Circuit Debugger and ICSP Programming Data. In-Circuit Debugger and ICSPTM Programming Clock. In-Circuit Debugger and ICSP Programming Data. Master Clear (Device Reset) Input. This line is brought low to cause a Reset. Output Compare/PWM Outputs. External Interrupt Inputs. Comparator Voltage Reference Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. Enable for On-Chip Voltage Regulator. Input Capture Inputs. Description Interrupt-on-Change Inputs.
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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TABLE 1-2:
Function PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMBE PMCS1 PMCS2 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin 30 29 8 6 5 4 16 22 32 31 28 27 24 23 51 45 44 60 61 62 63 64 1 2 3 53 52 80-Pin 36 35 10 8 7 6 24 23 40 39 34 33 30 29 63 57 56 76 77 78 79 80 1 2 3 67 66 100-Pin 44 43 14 12 11 10 29 28 50 49 42 41 35 34 78 71 70 93 94 98 99 100 3 4 5 82 81 I/O I/O I/O O O O O O O O O O O O O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST/TTL ST/TTL -- -- -- -- -- -- -- -- -- -- -- -- -- ST/TTL -- ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select 1 Strobe/Address bit 14. Parallel Master Port Chip Select 2 Strobe/Address bit 15. Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). Description Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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TABLE 1-2:
Function RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin -- -- -- -- -- -- -- -- -- -- -- -- 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- 39 47 48 40 80-Pin -- -- -- -- -- -- -- -- 23 24 52 53 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 4 -- 5 -- 49 59 60 50 100-Pin 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. PORTA Digital I/O. Description
TTL = TTL input buffer ANA = Analog level input/output
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TABLE 1-2:
Function RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF12 RF13 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 60 61 62 63 64 1 2 3 -- -- 58 59 34 33 31 32 35 -- -- -- -- 80-Pin 58 61 62 63 66 67 68 69 54 55 56 57 64 65 37 38 76 77 78 79 80 1 2 3 13 14 72 73 42 41 39 40 45 44 43 -- -- 100-Pin 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 55 54 53 40 39 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTF Digital I/O. PORTE Digital I/O. PORTD Digital I/O. Description
TTL = TTL input buffer ANA = Analog level input/output
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TABLE 1-2:
Function RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO SS1 SS2 T1CK T2CK T3CK T4CK T5CK TCK TDI TDO TMS Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin -- -- 37 36 4 5 6 8 -- -- -- -- 42 35 4 37 32 36 31 34 5 33 6 47 48 14 8 48 -- -- -- -- 27 28 24 23 80-Pin 75 74 47 46 6 7 8 10 -- -- -- -- 54 45 6 47 52 46 53 44 7 43 8 59 60 18 10 60 4 -- 5 -- 33 34 14 13 100-Pin 90 89 57 56 10 11 12 14 96 97 95 1 68 55 10 57 58 56 59 54 11 53 12 73 74 23 14 74 6 7 8 9 38 60 61 17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I I O O I O I/O I/O I I I I I I I O I Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST -- -- ST I2C I2C I2C IC ST ST -- -- ANA ANA ST ST ST ST ST ST ST ST ST -- ST
2
Description PORTG Digital I/O.
Real-Time Clock Alarm Output. SPI1 Serial Clock Output. SPI2 Serial Clock Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. SPI1 Serial Data Input. SPI2 Serial Data Input. SPI1 Serial Data Output. SPI2 Serial Data Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Slave Select Input/Frame Select Output (SPI1). Slave Select Input/Frame Select Output (SPI2). Timer1 Clock. Timer2 External Clock Input. Timer3 External Clock Input. Timer4 External Clock Input. Timer5 External Clock Input. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input.
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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TABLE 1-2:
Function U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDD VDDCAP VDDCORE VREFVREF+ VSS Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number 64-Pin 43 35 34 33 21 29 31 32 10, 26, 38 56 56 15 16 9, 25, 41 80-Pin 37 38 42 41 27 35 39 40 12, 32, 48 70 70 23 24 11, 31, 51 100-Pin 47 48 52 51 40 39 49 50 2, 16, 37, 46, 62 85 85 28 29 15, 36, 45, 65, 75 I/O I O I O I O I O P P P I I P Input Buffer ST -- ST DIG ST -- ST -- -- -- -- ANA ANA -- Description UART1 Clear to Send Input. UART1 Request to Send Output. UART1 Receive. UART1 Transmit Output. UART2 Clear to Send Input. UART2 Request to Send Output. UART 2 Receive Input. UART2 Transmit Output. Positive Supply for Peripheral Digital Logic and I/O Pins. External Filter Capacitor Connection (regulator enabled). Positive Supply for Microcontroller Core Logic (regulator disabled). A/D and Comparator Reference Voltage (Low) Input. A/D and Comparator Reference Voltage (High) Input. Ground Reference for Logic and I/O Pins.
TTL = TTL input buffer ANA = Analog level input/output
ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer
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NOTES:
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2.0
Note:
CPU
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 2. "CPU" (DS39703) in the "PIC24F Family Reference Manual" for more information.
For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three-parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports signed, unsigned and Mixed mode 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative, non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit (or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1.
The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen 16-bit working registers in the programmer's model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported either directly or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to 7 addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.
2.1
Programmer's Model
The programmer's model for the PIC24F is shown in Figure 2-2. All registers in the programmer's model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer's model are memory mapped.
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FIGURE 2-1:
PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCL PCH Program Counter Loop Stack Control Control Logic Logic Data RAM Address Latch 16 RAGU WAGU 16 Data Bus 16 16 Data Latch 16
PIC24F CPU CORE BLOCK DIAGRAM
23
Address Latch
Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX
Instruction Decode & Control
Instruction Reg
Control Signals to Various Blocks
Hardware Multiplier Divide Support
16 x 16 W Register Array 16
16-Bit ALU 16
To Peripheral Modules
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TABLE 2-1:
W0 through W15 PC SR SPLIM TBLPAG PSVPAG RCOUNT CORCON
CPU CORE REGISTERS
Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register
Register(s) Name
FIGURE 2-2:
PROGRAMMER'S MODEL
15 0 W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Frame Pointer Stack Pointer 0 Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM 22 PC 7 TBLPAG 7 PSVPAG 15 RCOUNT 15 SRH SRL
0 0 0 0
Stack Pointer Limit
Program Counter
Data Table Page Address 0 Program Space Visibility Page Address Repeat Loop Counter 0 STATUS Register (SR)
0
-- -- -- -- -- -- -- DC IPL RA N OV Z C 210
15
0 Core Control Register (CORCON)
-- -- -- -- -- -- -- -- -- -- -- -- IPL3 PSV -- --
Registers or bits shadowed for PUSH.S and POP.S instructions.
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2.2 CPU Control Registers
SR: CPU STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DC bit 8 R/W-0(1) IPL1(2) R/W-0(1) IPL0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0
REGISTER 2-1:
U-0 -- bit 15 R/W-0(1) IPL2(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred IPL2:IPL0: CPU Interrupt Priority Level Status bits(2) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: ALU Overflow bit 1 = Overflow occurred for signed (2's complement) arithmetic in this arithmetic operation 0 = No overflow has occurred Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the IPL when IPL3 = 1.
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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REGISTER 2-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/C-0 IPL3(1) R/W-0 PSV U-0 -- U-0 -- bit 0
CORCON: CORE CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as `0' User interrupts are disabled when IPL3 = 1.
bit 2
bit 1-0 Note 1:
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2.3 Arithmetic Logic Unit (ALU)
2.3.2 DIVIDER
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operation with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.
2.3.3
MULTI-BIT SHIFT SUPPORT
2.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned
The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2.
TABLE 2-2:
Instruction ASR SL LSR
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits.
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3.0 MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ128GA010 family of devices are shown in Figure 3-1.
3.1
Program Address Space
The program address memory space of PIC24FJ128GA010 family devices is 4M instructions. The space is addressable by a 24-bit value derived from
FIGURE 3-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES
PIC24FJ64GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (22K instructions) Flash Config Words
PIC24FJ96GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (32K instructions)
PIC24FJ128GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Memory Space
User Flash Program Memory (44K instructions)
00ABFEh 00AC00h 00FFFEh 010000h
Flash Config Words Flash Config Words Unimplemented (Read `0's) Unimplemented (Read `0's) Unimplemented (Read `0's)
0157FEh 015800h
7FFFFEh 800000h
Reserved
Reserved
Reserved
Configuration Memory Space
Device Configuration Registers
Device Configuration Registers
Device Configuration Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
FEFFFEh FF0000h FFFFFEh
Note:
Memory areas are not shown to scale.
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3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS
The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. In PIC24FJ128GA010 family devices, the top two words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ128GA010 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 23.1 "Configuration Bits".
3.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h. PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 "Interrupt Vector Table".
TABLE 3-1:
FLASH CONFIGURATION WORDS FOR PIC24FJ128GA010 FAMILY DEVICES
Program Memory (Words) 22,016 32,768 44,032 Configuration Word Addresses 00ABFCh: 00ABFEh 00FFFCh: 00FFFEh 0157FCh: 0157FEh
Device PIC24FJ64GA PIC24FJ96GA PIC24FJ128GA
FIGURE 3-2:
msw Address 000001h 000003h 000005h 000007h
PROGRAM MEMORY ORGANIZATION
most significant word 23 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') Instruction Width 16 least significant word 8 0 000000h 000002h 000004h 000006h PC Address (lsw Address)
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3.2
Note:
Data Address Space
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 3. "Data Memory" (DS39717) in the "PIC24F Family Reference Manual" for more information.
memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24FJ128GA010 family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned.
The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide, and point to bytes within the data space. This gives a data space address range of 64 Kbytes, or 32K words. The lower half of the data
3.2.1
DATA SPACE WIDTH
The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses.
FIGURE 3-3:
DATA SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES
MSB Address 0001h 07FFh 0801h MSB SFR Space LSB LSB Address 0000h 07FEh 0800h SFR Space Near Data Space
Implemented Data RAM
Data RAM 1FFFh 2001h 27FFh 2801h Unimplemented Read as `0' 7FFFh 8001h 7FFFh 8000h 1FFEh 2000h 27FEh 2800h
Program Space Visibility Area
FFFFh Note: Data memory areas are not shown to scale.
FFFEh
(c) 2009 Microchip Technology Inc.
DS39747E-page 29
PIC24FJ128GA010 FAMILY
3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT
To maintain backward compatibility with PIC(R) devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words.
3.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field.
3.2.4
SFR SPACE
The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30.
TABLE 3-2:
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address xx00 xx20 Core Timers I
2CTM
xx40 Capture
xx60 ICN -- SPI -- -- -- -- NVM/PMD
xx80 Compare -- -- -- -- -- --
xxA0 Interrupts -- -- -- -- -- -- --
xxC0 -- I/O -- -- -- I/O --
xxE0 -- -- -- -- -- --
000h 100h 200h 300h 400h 500h 600h 700h -- -- PMP --
UART A/D -- -- RTC/Comp -- -- -- -- CRC System
Legend: -- = No implemented SFRs in this block
DS39747E-page 30
(c) 2009 Microchip Technology Inc.
(c) 2009 Microchip Technology Inc. DS39747E-page 31
TABLE 3-3:
File Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT SR CORCON DISICNT Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052
CPU CORE REGISTERS MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Program Counter Low Word -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Repeat Loop Counter DC -- IPL2 -- IPL1 -- IPL0 -- RA -- N IPL3 OV PSV Z -- C -- Program Counter High Byte Table Page Address Pointer Program Memory Visibility Page Address Pointer
PIC24FJ128GA010 FAMILY
0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
Disable Interrupts Counter
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-4:
File Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C2 00C4
INTERRUPT CONTROLLER REGISTER MAP
Bit 15 NSTDIS ALTIVT -- U2TXIF -- -- -- -- U2TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 14 -- DISI -- U2RXIF -- RTCIF -- -- U2RXIE -- RTCIE -- T1IP2 T2IP2 -- CNIP2 -- T4IP2 U2TXIP2 -- IC5IP2 -- -- -- -- -- CRCIP2 Bit 13 -- -- AD1IF INT2IF PMPIF -- -- AD1IE INT2IE PMPIE -- -- T1IP1 T2IP1 -- CNIP1 -- T4IP1 U2TXIP1 -- IC5IP1 -- -- -- -- -- CRCIP1 Bit 12 -- -- U1TXIF T5IF -- -- -- U1TXIE T5IE -- -- -- T1IP0 T2IP0 -- CNIP0 -- T4IP0 U2TXIP0 -- IC5IP0 -- -- -- -- -- CRCIP0 Bit 11 -- -- U1RXIF T4IF -- -- -- U1RXIE T4IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 10 -- -- SPI1IF OC4IF -- -- -- SPI1IE OC4IE -- -- -- OC1IP2 OC2IP2 SPI1IP2 -- CMIP2 -- OC4IP2 -- IC4IP2 -- -- INT4IP2 RTCIP2 Bit 9 -- -- SPF1IF OC3IF OC5IF -- -- SPF1IE OC3IE OC5IE -- -- OC1IP1 OC2IP1 SPI1IP1 -- CMIP1 -- OC4IP1 -- IC4IP1 -- -- INT4IP1 RTCIP1 Bit 8 -- -- T3IF -- -- -- -- T3IE -- -- -- -- OC1IP0 OC2IP0 SPI1IP0 -- CMIP0 -- OC4IP0 -- IC4IP0 -- -- INT4IP0 RTCIP0 Bit 7 -- -- T2IF -- IC5IF -- -- T2IE -- IC5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 6 -- -- OC2IF -- IC4IF INT4IF -- OC2IE -- IC4IE INT4IE -- IC1IP2 IC2IP2 SPF1IP2 AD1IP2 -- OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 INT3IP2 -- Bit 5 -- -- IC2IF -- IC3IF INT3IF -- IC2IE -- IC3IE INT3IE -- IC1IP1 IC2IP1 SPF1IP1 AD1IP1 -- OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 INT3IP1 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- INT0EP INT0IF SI2C1IF SPF2IF -- -- INT0IE SI2C1IE SPF2IE -- -- INT0IP0 -- T3IP0 U1TXIP0 INT1IP0 -- T5IP0 SPF2IP0 -- -- -- -- -- -- -- All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 4440 0040 0040 0440 0440 0400 4440
DS39747E-page 32 (c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
MATHERR ADDRERR STKERR OSCFAIL INT4EP -- INT1IF -- -- -- -- INT1IE -- -- -- IC1IP0 IC2IP0 SPF1IP0 AD1IP0 -- OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2IP0 INT3IP0 -- U1ERIP0 INT3EP T1IF CNIF -- -- CRCIF T1IE CNIE -- -- CRCIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT2EP OC1IF CMIF -- MI2C2IF U2ERIF OC1IE CMIE -- MI2C2IE U2ERIE INT0IP2 -- T3IP2 U1TXIP2 INT1IP2 -- T5IP2 SPF2IP2 -- -- -- -- -- -- -- INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE INT0IP1 -- T3IP1 U1TXIP1 INT1IP1 -- T5IP1 SPF2IP1 -- -- -- -- -- -- --
U1RXIP2 U1RXIP1 U1RXIP0
MI2C1IP2 MI2C1IP1 MI2C1IP0
SI2C1IP2 SI2C1IP1 SI2C1IP0
U2RXIP2 U2RXIP1 U2RXIP0
MI2C2IP2 MI2C2IP1 MI2C2IP0
SI2C2IP2 SI2C2IP1
IPC15 IPC16 Legend:
U2ERIP2 U2ERIP1 U2ERIP0
U1ERIP2 U1ERIP1
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-5:
File Name Addr
ICN REGISTER MAP
Bit 15 CN15IE -- -- Bit 14 CN14IE -- -- Bit 13 CN13IE -- -- Bit 12 CN12IE -- -- Bit 11 CN11IE -- -- Bit 10 CN10IE -- -- Bit 9 CN9IE -- -- Bit 8 CN8IE -- -- Bit 7 CN7IE -- -- Bit 6 CN6IE -- -- Bit 5 CN5IE CN21IE(1) CN5PUE Bit 4 CN4IE CN20IE(1) CN4PUE Bit 3 CN3IE CN19IE(1) CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000
(c) 2009 Microchip Technology Inc. DS39747E-page 33
CNEN1 0060 CNEN2 0062 CNPU2 006A Legend: Note 1:
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE -- = unimplemented, read as `0'. Reset values are shown in hexadecimal Implemented in 80-pin and 100-pin devices only.
CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN17PUE CN16PUE
TABLE 3-6:
File Name TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON TMR4 TMR5HLD TMR5 PR4 PR5 T4CON T5CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120
TIMER REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF
Timer1 Register Period Register 1 TON -- TSIDL -- -- -- -- -- -- TGATE TCKPS1 TCKPS0 -- TSYNC TCS -- Timer2 Register Timer3 Holding Register (For 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- -- TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 -- -- -- TCS TCS -- --
PIC24FJ128GA010 FAMILY
0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF
Timer4 Register Timer5 Holding Register (For 32-bit operations only) Timer5 Register Period Register 4 Period Register 5 TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- -- TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 -- -- -- TCS TCS -- --
0000 0000
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-7:
File Name IC1BUF IC1CON IC2BUF IC2CON IC3BUF IC3CON IC4BUF IC4CON IC5BUF IC5CON Legend: Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152
INPUT CAPTURE REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI1 ICI1 ICI1 ICI1 ICI1 ICI0 ICI0 ICI0 ICI0 ICI0 ICOV ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICBNE ICM2 ICM2 ICM2 ICM2 ICM2 ICM1 ICM1 ICM1 ICM1 ICM1 ICM0 ICM0 ICM0 ICM0 ICM0 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000
DS39747E-page 34 (c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
Input 1 Capture Register -- -- -- -- -- -- -- -- -- -- ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ICTMR ICTMR ICTMR ICTMR ICTMR Input 2 Capture Register Input 3 Capture Register Input 4 Capture Register Input 5 Capture Register
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-8:
File Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON OC5RS OC5R OC5CON Legend: Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 0198 019A 019C
OUTPUT COMPARE REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx -- OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx -- OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx -- OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx -- OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx -- OCFLT OCTSEL OCM2 OCM1 OCM0 0000
Output Compare 1 Secondary Register Output Compare 1 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 2 Secondary Register Output Compare 2 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 3 Secondary Register Output Compare 3 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 4 Secondary Register Output Compare 4 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 5 Secondary Register Output Compare 5 Register -- -- OCSIDL -- -- -- -- -- -- --
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
(c) 2009 Microchip Technology Inc. DS39747E-page 35
TABLE 3-9:
File Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C
I2C1 REGISTER MAP
Bit 15 -- -- -- I2CEN ACKSTAT -- -- Bit 14 -- -- -- -- TRSTAT -- -- Bit 13 -- -- -- I2CSIDL -- -- -- Bit 12 -- -- -- SCLREL -- -- -- Bit 11 -- -- -- IPMIEN -- -- -- Bit 10 -- -- -- A10M BCL -- -- Bit 9 -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 -- -- ACKDT D/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R/W RSEN RBF SEN TBF 1000 0000 0000 0000
Receive Register Transmit Register Baud Rate Generator ACKEN P RCEN S
Address Register Address Mask
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-10:
File Name I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK Legend: Addr 0210 0212 0214 0216 0218 021A 021C
I2C2 REGISTER MAP
Bit 15 -- -- -- I2CEN ACKSTAT -- -- Bit 14 -- -- -- -- TRSTAT -- -- Bit 13 -- -- -- I2CSIDL -- -- -- Bit 12 -- -- -- SCLREL -- -- -- Bit 11 -- -- -- IPMIEN -- -- -- Bit 10 -- -- -- A10M BCL -- -- Bit 9 -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2CPOV Bit 8 -- -- ACKDT D/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R/W RSEN RBF SEN TBF 1000 0000 0000 0000 S
PIC24FJ128GA010 FAMILY
Receive Register Transmit Register Baud Rate Generator ACKEN P RCEN
Address Register Address Mask
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-11:
File Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: Addr 0220 0222 0224 0226 0228
UART1 REGISTER MAP
Bit 15 UARTEN UTXISEL1 -- -- Bit 14 -- TXINV -- -- Bit 13 USIDL UTXISEL0 -- -- Bit 12 IREN -- -- -- Bit 11 RTSMD UTXBRK -- -- Bit 10 -- UTXEN -- -- Bit 9 UEN1 UTXBF -- -- Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 RXINV RIDLE Bit 3 BRGH PERR Bit 2 PDSEL1 FERR Bit 1 PDSEL0 OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000
DS39747E-page 36 (c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
URXISEL1 URXISEL0
Transmit Register Receive Register
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-12:
File Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: Addr 0230 0232 0234 0236 0238
UART2 REGISTER MAP
Bit 15 UARTEN UTXISEL1 -- -- Bit 14 -- TXINV -- -- Bit 13 USIDL UTXISEL0 -- -- Bit 12 IREN -- -- -- Bit 11 RTSMD UTXBRK -- -- Bit 10 -- UTXEN -- -- Bit 9 UEN1 UTXBF -- -- Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 RXINV RIDLE Bit 3 BRGH PERR Bit 2 PDSEL1 FERR Bit 1 PDSEL0 OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000
URXISEL1 URXISEL0
Transmit Register Receive Register
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-13:
File Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: Addr 0240 0242 0244 0248
SPI1 REGISTER MAP
Bit 15 SPIEN -- FRMEN Bit 14 -- -- SPIFSD Bit 13 SPISIDL -- SPIFPOL Bit 12 -- DISSCK -- Bit 11 -- DISSDO -- Bit 10 Bit 9 Bit 8 Bit 7 SRMPT SSEN -- Bit 6 SPIROV CKP -- Bit 5 SRXMPT MSTEN -- Bit 4 SISEL2 SPRE2 -- Bit 3 SISEL1 SPRE1 -- Bit 2 SISEL0 SPRE0 -- Bit 1 SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000
SPIBEC2 SPIBEC1 SPIBEC0 MODE16 -- SMP -- CKE --
SPI1 Transmit and Receive Buffer
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-14:
File Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: Addr 0260 0262 0264 0268
SPI2 REGISTER MAP
Bit 15 SPIEN -- FRMEN Bit 14 -- -- SPIFSD Bit 13 SPISIDL -- SPIFPOL Bit 12 -- DISSCK -- Bit 11 -- DISSDO -- Bit 10 Bit 9 Bit 8 Bit 7 SRMPT SSEN -- Bit 6 SPIROV CKP -- Bit 5 SRXMPT MSTEN -- Bit 4 SISEL2 SPRE2 -- Bit 3 SISEL1 SPRE1 -- Bit 2 SISEL0 SPRE0 -- Bit 1 SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000
SPIBEC2 SPIBEC1 SPIBEC0 MODE16 -- SMP -- CKE --
SPI2 Transmit and Receive Buffer
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-15:
File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0328 032C 0330
ADC REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC1 -- ADCS6 -- PCFG6 CSSL6 SSRC0 SMPI3 ADCS5 -- PCFG5 CSSL5 -- SMPI2 ADCS4 -- PCFG4 CSSL4 -- SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0 0000 0000 0000 0000 0000 0000
(c) 2009 Microchip Technology Inc. DS39747E-page 37
ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADON VCFG2 ADRC CH0NB PCFG15 CSSL15 -- VCFG1 -- -- PCFG14 CSSL14 ADSIDL VCFG0 -- -- PCFG13 CSSL13 -- r SAMC4 -- PCFG12 CSSL12 -- -- SAMC3 CH0SB3 PCFG11 CSSL11 -- CSCNA SAMC2 CH0SB2 PCFG10 CSSL10 FORM1 -- SAMC1 CH0SB1 PCFG9 CSSL9 FORM0 -- SAMC0 CH0SB0 PCFG8 CSSL8 SSRC2 BUFS ADCS7 CH0NA PCFG7 CSSL7
PIC24FJ128GA010 FAMILY
x = unknown value on Reset, -- = unimplemented, read as `0', r = reserved, maintain as `0'. Reset values are shown in hexadecimal.
TABLE 3-16:
File Name TRISA PORTA LATA ODCA Legend: Note 1: 2: Addr 02C0 02C2 02C4 06C0
PORTA REGISTER MAP
Bit 15 Bit 14 Bit 13 -- -- -- -- Bit 12 -- -- -- -- Bit 11 -- -- -- -- Bit 10 Bit 9 Bit 8 -- -- -- -- Bit 7 TRISA7 RA7 LATA7 ODA7) Bit 6 TRISA6 RA6 LATA6 ODA6 Bit 5 TRISA5(2) RA5
(2)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets C6FF xxxx xxxx 0000
TRISA15(1) TRISA14(1) RA15(1) LATA15(1) ODA15(1) RA14
(1)
TRISA10(1) TRISA9(1) RA10
(1)
TRISA4(2) TRISA3(2) TRISA2(2) TRISA1(2) TRISA0(2) RA4(2) LATA4(2) ODA4(2) RA3(2) LATA3(2) ODA3(2) RA2(2) LATA2(2) ODA2(2) RA1(2) LATA1(2) ODA1(2) RA0(2) LATA0(2) ODA0(2)
RA9
(1)
LATA14(1) ODA14(1)
LATA10(1) ODA10(1)
LATA9(1) ODA9(1)
LATA5(2) ODA5(2)
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. Implemented in 100-pin devices only.
DS39747E-page 38 (c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 3-17:
File Name TRISB PORTB LATB ODCB Legend: Note 1: Addr 02C6 02C8 02CA 06C6
PORTB REGISTER MAP
Bit 15 TRISB15 RB15 LATB15 ODB15 Bit 14 TRISB14 RB14 LATB14 ODB14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 TRISB9 RB9 LATB9 ODB9 Bit 8 TRISB8 RB8 LATB8 ODB8 Bit 7 TRISB7 RB7 LATB7 ODB7 Bit 6 TRISB6 RB6 LATB6 ODB6 Bit 5 TRISB5 RB5 LATB5 ODB5 Bit 4 TRISB4 RB4 LATB4 ODB4 Bit 3 TRISB3 RB3 LATB3 ODB3 Bit 2 TRISB2 RB2 LATB2 ODB2 Bit 1 TRISB1 RB1 LATB1 ODB1 Bit 0 TRISB0 RB0 LATB0 ODB0 All Resets FFFF xxxx xxxx 0000
TRISB13(1) TRISB12(1) TRISB11(1) TRISB10(1) RB13(1) LATB13(1) ODB13(1) RB12(1) LATB12(1) ODB12(1) RB11(1) LATB11(1) ODB11(1) RB10(1) LATB10(1) ODB10(1)
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices Unimplemented when JTAG is enabled.
TABLE 3-18:
File Name TRISC PORTC LATC ODCC Legend: Note 1: 2: Addr 02CC 02CE 02D0 06CC
PORTC REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 -- -- -- -- Bit 8 -- -- -- -- Bit 7 -- -- -- -- Bit 6 -- -- -- -- Bit 5 -- -- -- -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- -- All Resets F01E xxxx xxxx 0000
TRISC15 TRISC14 TRISC13 TRISC12 RC15 LATC15 ODC15 RC14 LATC14 ODC14 RC13 LATC13 ODC13 RC12 LATC12 ODC12
TRISC4(2) TRISC3(1) TRISC2(2) TRISC1(1) RC4(2) LATC4(2) ODC4(2) RC3(1) LATC3(1) ODC3(1) RC2(2) LATC2(2) ODC2(2) RC1(1) LATC1(1) ODC1(1)
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. Implemented in 100-pin devices only
TABLE 3-19:
File Name TRISD PORTD LATD ODCD Legend: Note 1: Addr 02D2 02D4 02D6 06D2
PORTD REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TRISD11 RD11 LATD11 ODD11 Bit 10 TRISD10 RD10 LATD10 ODD10 Bit 9 TRISD9 RD9 LATD9 ODD9 Bit 8 TRISD8 RD8 LATD8 ODD8 Bit 7 TRISD7 RD7 LATD7 ODD7 Bit 6 TRISD6 RD6 LATD6 ODD6 Bit 5 TRISD5 RD5 LATD5 ODD5 Bit 4 TRISD4 RD4 LATD4 ODD4 Bit 3 TRISD3 RD3 LATD3 ODD3 Bit 2 TRISD2 RD2 LATD2 ODD2 Bit 1 TRISD1 RD1 LATD1 ODD1 Bit 0 TRISD0 RD0 LATD0 ODD0 All Resets FFFF xxxx xxxx 0000
TRISD15(1) TRISD14(1) TRISD13(1) TRISD12(1) RD15(1) LATD15(1) ODD15(1) RD14(1) LATD14(1) ODD14(1) RD13(1) LATD13(1) ODD13(1) RD12(1) LATD12(1) ODD12(1)
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only.
TABLE 3-20:
File Name TRISE PORTE LATE ODCE Legend: Note 1: Addr 02D8 02DA 02DC 06D8
PORTE REGISTER MAP
Bit 15 -- -- -- -- Bit 14 -- -- -- -- Bit 13 -- -- -- -- Bit 12 -- -- -- -- Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 Bit 8 Bit 7 TRISE7 RE7 LATE7 ODE7 Bit 6 TRISE6 RE6 LATE6 ODE6 Bit 5 TRISE5 RE5 LATE5 ODE5 Bit 4 TRISE4 RE4 LATE4 ODE4 Bit 3 TRISE3 RE3 LATE3 ODE3 Bit 2 TRISE2 RE2 LATE2 ODE2 Bit 1 TRISE1 RE1 LATE1 ODE1 Bit 0 TRISE0 RE0 LATE0 ODE0 All Resets 03FF xxxx xxxx 0000
(c) 2009 Microchip Technology Inc. DS39747E-page 39
TRISE9(1) TRISE8(1) RE9(1) LATE9(1) ODE9(1) RE8(1) LATE8(1) ODE8(1)
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only.
TABLE 3-21:
File Name TRISF PORTF LATF ODCF Legend: Note 1: 2: Addr 02DE 02E0 02E2 06DE
PORTF REGISTER MAP
Bit 15 -- -- -- -- Bit 14 -- -- -- -- Bit 13 TRISF13(
1)
Bit 12 TRISF12(
1)
Bit 11 -- -- -- --
Bit 10 -- -- -- --
Bit 9 -- -- -- --
Bit 8
Bit 7
Bit 6 TRISF6 RF6 LATF6 ODF6
Bit 5 TRISF5 RF5 LATF5 ODF5
Bit 4 TRISF4 RF4 LATF4 ODF4
Bit 3 TRISF3 RF3 LATF3 ODF3
Bit 2 TRISF2 RF2 LATF2 ODF2
Bit 1 TRISF1 RF1 LATF1 ODF1
Bit 0 TRISF0 RF0 LATF0 ODF0
All Resets 31FF xxxx xxxx 0000
TRISF8(2 TRISF7(2
) )
RG13(1) ODF13(1)
RG12(1) ODF12(1)
RF8(2) LATF8(2) ODF8(2)
RF7(2) LATF7(2) ODF7(2)
PIC24FJ128GA010 FAMILY
LATF13(1) LATF12(1)
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only.
TABLE 3-22:
File Name TRISG PORTG LATG ODCG Legend: Note 1: 2: Addr 02E4 02E6 02E8 06E4
PORTG REGISTER MAP
Bit 15 TRISG15 RG15 LATG15 ODG15 Bit 14 Bit 13 Bit 12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 TRISG9 RG9 LATG9 ODG9 Bit 8 Bit 7 Bit 6 TRISG6 RG6 LATG6 ODG6 Bit 5 -- -- -- -- Bit 4 -- -- -- -- Bit 3 TRISG3 RG3 LATG3 ODG3 Bit 2 TRISG2 RG2 LATG2 ODG2 Bit 1 Bit 0 All Resets F3CF xxxx xxxx 0000
TRISG14(1) TRISG13(1) TRISG12(1 RG14(1) LATG14(1) ODG14(1) RG13(1) LATG13(1) ODG13(1) RG12(1) LATG12(1) ODG12(1)
TRISG8 TRISG7 RG8 LATG8 ODG8 RG7 LATG7 ODG7
TRISG1(2) TRISG0(2) RG1(2) LATG1(2) ODG1(2) RG0(2) LATG0(2) ODG0(2)
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only.
TABLE 3-23:
File Name PADCFG1 Legend: Addr 02FC
PAD CONFIGURATION MAP
Bit 15 -- Bit 14 -- Bit 13 -- Bit 12 -- Bit 11 -- Bit 10 -- Bit 9 -- Bit 8 -- Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 RTSECSEL Bit 0 PMPTTL All Resets 0000
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices.
TABLE 3-24:
File Name PMCON PMMODE PMADDR(1) PMDOUT1(1) PMDOUT2 PMDIN1 PMDIN2 PMAEN PMSTAT Legend: Note 1: Addr 0600 0602 0604 0606 0608 060A 060C 060E
PARALLEL MASTER/SLAVE PORT REGISTER MAP
Bit 15 PMPEN BUSY CS2 Bit 14 -- IRQM1 CS1 Bit 13 PSIDL IRQM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 CSF1 WAITB1 Bit 6 CSF0 WAITB0 Bit 5 ALP WAITM3 Bit 4 CS2P WAITM2 Bit 3 CS1P WAITM1 Bit 2 BEP WAITM0 Bit 1 WRSP WAITE1 Bit 0 RDSP WAITE0 All Resets 0000 0000 0000 0000 0000 0000 0000 PTEN5 -- PTEN4 -- PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E 0000 008F
DS39747E-page 40 (c) 2009 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN INCM1 INCM0 MODE16 MODE1 MODE0
Parallel Port Destination Address<13:0> (Master modes) Parallel Port Data Out Register 1 (Buffers 0 and 1) Parallel Port Data Out Register 2 (Buffers 2 and 3) Parallel Port Data In Register 1 (Buffers 0 and 1) Parallel Port Data In Register 2 (Buffers 2 and 3)
PTEN15 IBF
PTEN14 IBOV
PTEN13 --
PTEN12 --
PTEN11 IB3F
PTEN10 IB2F
PTEN9 IB1F
PTEN8 IB0F
PTEN7 OBE
PTEN6 OBUF
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes, and as PMADDR only in Master modes.
TABLE 3-25:
File Name ALRMVAL ALCFGRPT RTCVAL RCFGCAL(1) Legend: Note 1: Addr 0620 0622 0624 0626
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ARPT5 CAL5 ARPT4 CAL4 ARPT3 CAL3 ARPT2 CAL2 ARPT1 CAL1 ARPT0 CAL0 0000 xxxx 0000
Alarm Value Register Window Based on ALRMPTR<1:0> ALRMEN RTCEN CHIME -- AMASK3 AMASK2 AMASK1 AMASK0 RTCOE ALRMPTR1 ALRMPTR0 RTCPTR1 RTCPTR0 ARPT7 CAL7 ARPT6 CAL6 RTCC Value Register Window Based on RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. RCFGCAL register Reset value dependent on type of Reset.
TABLE 3-26:
File Name CMCON CVRCON Legend: Addr 0630 0632
DUAL COMPARATOR REGISTER MAP
Bit 15 CMIDL -- Bit 14 -- -- Bit 13 C2EVT -- Bit 12 C1EVT -- Bit 11 C2EN -- Bit 10 C1EN -- Bit 9 C2OUTEN -- Bit 8 C1OUTEN -- Bit 7 C2OUT CVREN Bit 6 C1OUT CVROE Bit 5 C2INV CVRR Bit 4 C1INV CVRSS Bit 3 C2NEG CVR3 Bit 2 C2POS CVR2 Bit 1 C1NEG CVR1 Bit 0 C1POS CVR0 All Resets 0000 0000
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-27:
File Name CRCCON CRCXOR CRCDAT CRCWDAT Legend: Addr 0640 0642 0644 0646
CRC REGISTER MAP
Bit 15 -- Bit 14 -- Bit 13 CSIDL Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 -- Bit 4 CRCGO Bit 3 PLEN3 Bit 2 PLEN2 Bit 1 PLEN1 Bit 0 PLEN0 All Resets 0000 0000 0000 0000
(c) 2009 Microchip Technology Inc. DS39747E-page 41
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRC XOR Polynomial Register CRC Data Input Register CRC Result Register
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 3-28:
File Name RCON OSCCON CLKDIV OSCTUN Legend: Note 1: 2: Addr 0740 0742 0744 0748
SYSTEM REGISTER MAP
Bit 15 TRAPR -- ROI -- Bit 14 IOPUWR COSC2 DOZE2 -- Bit 13 -- COSC1 DOZE1 -- Bit 12 -- COSC0 DOZE0 -- Bit 11 -- -- DOZEN -- Bit 10 -- NOSC2 RCDIV2 -- Bit 9 CM NOSC1 RCDIV1 -- Bit 8 VREGS NOSC0 RCDIV0 -- Bit 7 EXTR CLKLOCK -- -- Bit 6 SWR -- -- -- Bit 5 SWDTEN LOCK -- Bit 4 WDTO -- -- Bit 3 SLEEP CF -- Bit 2 IDLE -- -- Bit 1 BOR SOSCEN -- Bit 0 POR OSWEN -- All Resets xxxx(1) xxxx(2) 0100 0000
PIC24FJ128GA010 FAMILY
TUN<5:0>
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 3-29:
File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766
NVM REGISTER MAP
Bit 15 WR -- Bit 14 WREN -- Bit 13 WRERR -- Bit 12 -- -- Bit 11 -- -- Bit 10 -- -- Bit 9 -- -- Bit 8 -- -- Bit 7 -- Bit 6 ERASE Bit 5 -- Bit 4 -- Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000(1) 0000
NVMOP3 NVMOP2 NVMOP1 NVMOP0
NVMKEY<7:0>
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 3-30:
File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774
PMD REGISTER MAP
Bit 15 T5MD -- -- Bit 14 T4MD -- -- Bit 13 T3MD -- -- Bit 12 T2MD IC5MD -- Bit 11 T1MD IC4MD -- Bit 10 -- IC3MD Bit 9 -- IC2MD Bit 8 -- IC1MD PMPMD Bit 7 I2C1MD -- CRCPMD Bit 6 U2MD -- -- Bit 5 U1MD -- -- Bit 4 SPI2MD OC5MD -- Bit 3 SPI1MD OC4MD -- Bit 2 -- OC3MD -- Bit 1 -- OC2MD I2C2MD Bit 0 ADC1MD OC1MD -- All Resets 0000 0000 0000
CMPMD RTCCMD
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
PIC24FJ128GA010 FAMILY
3.2.5 SOFTWARE STACK
3.3
In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push.
Interfacing Program and Data Memory Spaces
The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word.
The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.
3.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is `1', PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.
FIGURE 3-4:
0000h 15
CALL STACK FRAME
0
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16>
W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++]
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(c) 2009 Microchip Technology Inc.
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TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note 1: User 0 0 Program Space Address <23> 0 TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> 0xx xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx <14:1> <0> 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
0
Program Counter 23 bits EA
0
1/0
Table Operations(2)
1/0
TBLPAG 8 bits 24 bits 16 bits
Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 bits
1
EA
0
15 bits 23 bits
User/Configuration Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as `0' in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.
(c) 2009 Microchip Technology Inc.
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3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the "phantom byte", will always be `0'. In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be `0' when the upper "phantom" byte is selected (byte select = 1).
The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is `1'; the lower byte is selected when it is `0'.
In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the Table Page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the Device ID. Table write operations are not allowed.
FIGURE 3-6:
TBLPAG 02
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 23 15 0 000000h
00000000 00000000 00000000 00000000
23
16
8
0
020000h 030000h
`Phantom' Byte
TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.
800000h
DS39747E-page 44
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3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with `1111 1111' or `0000 0000' to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes.
The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is `1' and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the
For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
Program Space
PSVPAG 02 23 15 0 000000h 010000h 018000h The data in the page designated by PSVPAG is mapped into the upper half of the data memory space....
Data Space
0000h Data EA<14:0>
8000h
PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.
FFFFh
800000h
(c) 2009 Microchip Technology Inc.
DS39747E-page 45
PIC24FJ128GA010 FAMILY
NOTES:
DS39747E-page 46
(c) 2009 Microchip Technology Inc.
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4.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 4. "Program Memory" (DS39715) in the "PIC24F Family Reference Manual" for more information.
controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time.
The PIC24FJ128GA010 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in four ways: 1. 2. 3. 4. In-Circuit Serial ProgrammingTM (ICSPTM) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP)
4.1
Table Instructions and Flash Programming
Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG<7:0> bits and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.
ICSP allows a PIC24FJ128GA010 family device to be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGCx and PGDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the micro-
FIGURE 4-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits Using Program Counter 0 Program Counter 0
Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 Bits 16 Bits
User/Configuration Space Select
24-Bit EA
Byte Select
(c) 2009 Microchip Technology Inc.
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4.2 RTSP Operation 4.4
The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 64 TBLWT instructions are required to write the full row of memory. To ensure that no data is corrupted during a write, any unused addresses should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing is not recommended.
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses an onboard bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. See the device programming specification for more information on Enhanced ICSP
4.5
Control Registers
There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.6 "Programming Operations" for further details.
4.6
Programming Operations
A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or an erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. Configuration Word values are stored in the last two locations of program memory. Performing a page erase operation on the last page of program memory clears these values and enables code protection. As a result, avoid performing page erase operations on the last page of program memory.
All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row
4.3
JTAG Operation
The PIC24F family supports JTAG programming and boundary scan. Boundary scan can improve the manufacturing process by verifying pin to PCB connectivity. Programming can be performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
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REGISTER 4-1:
R/SO-0(1) WR bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Settable-Only bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 -- U-0 -- R/W-0(1) NVMOP3
(2)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WREN R/W-0(1) WRERR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0(1) NVMOP2
(2)
R/W-0(1) NVMOP1
(2)
R/W-0(1) NVMOP0(2) bit 0
WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as `0' ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command 0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command Unimplemented: Read as `0' NVMOP3:NVMOP0: NVM Operation Select bits(2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) These bits can only be reset on POR. All other combinations of NVMOP3:NVMOP0 are unimplemented. Available in ICSPTM mode only. Refer to device programming specification.
bit 14
bit 13
bit 12-7 bit 6
bit 5-4 bit 3-0
Note 1: 2: 3:
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4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY
4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON<3:0>) to `0010' to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). Write the program block to Flash memory: a) Set the NVMOP bits to `0001' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.
6.
For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3.
EXAMPLE 4-1:
ERASING A PROGRAM MEMORY BLOCK
; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ;
; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR
Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority <7 for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted
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EXAMPLE 4-2: LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] * * * ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0]
EXAMPLE 4-3:
DISI MOV MOV MOV MOV BSET BTSC BRA #5
INITIATING A PROGRAMMING SEQUENCE
; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; ; Write the 55 key Write the AA key Start the program/erase sequence and wait for it to be completed #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR NVMCON, #15 $-2
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4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
If a Flash location has been erased, it can be programmed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to `0011'. The write is performed by executing the unlock sequence and setting the WR bit.
EXAMPLE 4-4:
PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
; Setup a pointer to data Program Memory MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ;Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address MOV MOV TBLWTL TBLWTH #LOW_WORD_N, W2 #HIGH_BYTE_N, W3 W2, [W0] W3, [W0++] ; ; ; Write PM low word into program latch ; Write PM high byte into program latch
; Setup NVMCON for programming one word to data Program Memory MOV #0x4003, W0 ; MOV W0, NVMCON ; Set NVMOP bits to 0011 DISI MOV MOV MOV MOV BSET #5 #0x55, W0 W0, NVMKEY #0xAA, W0 W0, NVMKEY NVMCON, #WR ; Disable interrupts while the KEY sequence is written ; Write the key sequence
; Start the write cycle
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5.0
Note:
RESETS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 7. "Reset" (DS39712) in the "PIC24F Family Reference Manual" for more information.
Note:
Refer to the specific peripheral or CPU section of this manual for register Reset states.
The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * * * POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset CM: Configuration Word Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset
All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits except for the BOR and POR bits (RCON<1:0>), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.
A simplified block diagram of the Reset module is shown in Figure 5-1. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise Detect VDD Brown-out Reset POR SYSRST
BOR
Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized W Register Configuration Word Mismatch Reset
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REGISTER 5-1:
R/W-0 TRAPR bit 15 R/W-0 EXTR bit 7 Legend: R = Readable bit -n = Value at POR bit 15
RCON: RESET CONTROL REGISTER(1)
R/W-0 IOPUWR U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CM R/W-0 VREGS bit 8 R/W-1 POR bit 0
R/W-0 SWR
R/W-0 SWDTEN(2)
R/W-0 WDTO
R/W-0 SLEEP
R/W-0 IDLE
R/W-1 BOR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14
bit 13-10 bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as `0' CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred VREGS: Voltage Regulator Standby Enable bit 1 = Regulator remains active during Sleep 0 = Regulator goes to standby during Sleep EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
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TABLE 5-1: RESET FLAG BIT OPERATION
Setting Event Trap conflict event Illegal opcode or uninitialized W register access MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR POR POR POR POR PWRSAV instruction, POR POR POR -- -- Clearing Event Flag Bit TRAPR (RCON<15>) IOPUWR (RCON<14>) EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note:
All Reset flag bits may be set or cleared by the user software.
5.1
Clock Source Selection at Reset
5.2
Device Reset Times
If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to 7.0 "Oscillator Configuration" for further details.
The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time that the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.
TABLE 5-2:
OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED)
Clock Source Determinant Oscillator Configuration bits (FNOSC2:FNOSC0) COSC Control bits (OSCCON<14:12>)
Reset Type POR BOR MCLR WDTR SWR
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TABLE 5-3:
Reset Type POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Clock Source SYSRST Delay System Clock Delay -- TLOCK TOST TOST + TLOCK -- TLOCK TOST TOST + TLOCK -- -- -- -- -- -- FSCM Delay -- TFSCM TFSCM TFSCM -- TFSCM TFSCM TFSCM -- -- -- -- -- -- Notes 1, 2, 3 1, 2, 3, 5, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 5, 6 2, 3 2, 3, 5, 6 2, 3, 4, 6 2, 3, 4, 5, 6 3 3 3 3 3 3
EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TRST TRST TRST TRST TRST TRST
BOR
EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL
MCLR WDT Software Illegal Opcode Uninitialized W Trap Conflict Note 1: 2: 3: 4: 5: 6:
Any Clock Any Clock Any Clock Any Clock Any Clock Any Clock
TPOR = Power-on Reset delay (10 s nominal). TSTARTUP = TVREG (10 s nominal) if on-chip regulator enabled or TPWRT (64 ms nominal) if on-chip regulator disabled. TRST = Internal state Reset time (20 s nominal). TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. TLOCK = PLL lock time. TFSCM = Fail-Safe Clock Monitor delay (100 s nominal).
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5.2.1 POR AND LONG OSCILLATOR START-UP TIMES
5.3
Special Function Register Reset States
The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: * The oscillator circuit has not begun to oscillate. * The Oscillator Start-up Timer has NOT expired (if a crystal oscillator is used). * The PLL has not achieved a LOCK (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known.
Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Device Configuration register (see Table 5-2). The RCFGCAL and NVMCON registers are only affected by a POR.
5.2.2
FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine.
5.2.2.1
FSCM Delay for Crystal and PLL Clock Sources
When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay, TFSCM, will automatically be inserted after the POR and PWRT delay times. The FSCM will not begin to monitor the system clock source until this delay expires. The FSCM delay time is nominally 100 s and provides additional time for the oscillator and/or PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled.
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NOTES:
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6.0
Note:
INTERRUPT CONTROLLER
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 8. "Interrupts" (DS39707) in the "PIC24F Family Reference Manual" for more information.
6.1.1
ALTERNATE INTERRUPT VECTOR TABLE
The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU. It has the following features: Up to 8 processor exceptions and software traps 7 user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors A unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Alternate Interrupt Vector Table (AIVT) for debug support * Fixed interrupt entry and return latencies * * * *
The Alternate Interrupt Vector Table (AIVT) is located after the IVT as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT.
6.2
Reset Sequence
6.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 6-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24FJ128GA010 family devices implement nonmaskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2.
A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F device clears its registers in response to a Reset which forces the PC to zero. The microcontroller then begins program execution at location 000000h. The user programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.
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FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE
Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Start of Code 000000h 000002h 000004h
000014h
Decreasing Natural Order Priority
00007Ch 00007Eh 000080h
Interrupt Vector Table (IVT)(1)
0000FCh 0000FEh 000100h 000102h
000114h
Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h
0001FEh 000200h
Note 1:
See Table 6-2 for the interrupt vector list.
TABLE 6-1:
0 1 2 3 4 5 6 7
TRAP VECTOR DETAILS
IVT Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 0001172h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved
(c) 2009 Microchip Technology Inc.
Vector Number
Trap Source
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS
Vector Number 13 18 67 0 20 29 53 54 17 16 50 49 1 5 37 38 39 19 2 6 25 26 41 45 62 9 10 32 33 3 7 8 27 28 65 11 12 66 30 31 IVT Address 00002Eh 000038h 00009Ah 000014h 00003Ch 00004Eh 00007Eh 000080h 000036h 000034h 000078h 000076h 000016h 00001Eh 00005Eh 000060h 000062h 00003Ah 000018h 000020h 000046h 000048h 000066h 00006Eh 000090h 000026h 000028h 000054h 000056h 00001Ah 000022h 000024h 00004Ah 00004Ch 000096h 00002Ah 00002Ch 000098h 000050h 000052h AIVT Address 00012Eh 000138h 00019Ah 000114h 00013Ch 00014Eh 00017Eh 000180h 000136h 000034h 000178h 000176h 000116h 00011Eh 00015Eh 000160h 000162h 00013Ah 000118h 000120h 000146h 000148h 000166h 00016Eh 000190h 000126h 000128h 000154h 000156h 00011Ah 000122h 000124h 00014Ah 00014Ch 000196h 00012Ah 00012Ch 000198h 000150h 000152h Interrupt Bit Locations Flag IFS0<13> IFS1<2> IFS4<3> IFS0<0> IFS1<4> IFS1<13> IFS3<5> IFS3<6> IFS1<1> IFS1<0> IFS3<2> IFS3<1> IFS0<1> IFS0<5> IFS2<5> IFS2<6> IFS2<7> IFS1<3> IFS0<2> IFS0<6> IFS1<9> IFS1<10> IFS2<9> IFS2<13> IFS3<14> IFS0<9> IFS0<10> IFS2<0> IFS2<1> IFS0<3> IFS0<7> IFS0<8> IFS1<11> IFS1<12> IFS4<1> IFS0<11> IFS0<12> IFS4<2> IFS1<14> IFS1<15> Enable IEC0<13> IEC1<2> IEC4<3> IEC0<0> IEC1<4> IEC1<13> IEC3<5> IEC3<6> IEC1<1> IEC1<0> IEC3<2> IEC3<1> IEC0<1> IEC0<5> IEC2<5> IEC2<6> IEC2<7> IEC1<3> IEC0<2> IEC0<6> IEC1<9> IEC1<10> IEC2<9> IEC2<13> IEC3<13> IEC0<9> IEC0<10> IEC0<0> IEC2<1> IEC0<3> IEC0<7> IEC0<8> IEC1<11> IEC1<12> IEC4<1> IEC0<11> IEC0<12> IEC4<2> IEC1<14> IEC1<15> Priority IPC3<6:4> IPC4<10:8> IPC16<14:12> IPC0<2:0> IPC5<2:0> IPC7<6:4> IPC13<6:4> IPC13<10:8> IPC4<6:4> IPC4<2:0> IPC12<10:8> IPC12<6:4> IPC0<6:4> IPC1<6:4> IPC9<6:4> IPC9<10:8> IPC9<14:12> IPC4<14:12> IPC0<10:8> IPC1<10:8> IPC6<6:4> IPC6<10:8> IPC10<6:4> IPC11<6:4> IPC15<10:8> IPC2<6:4> IPC2<10:8> IPC8<2:0> IPC8<6:4> IPC0<14:12> IPC1<14:12> IPC2<2:0> IPC6<14:12> IPC7<2:0> IPC16<6:4> IPC2<14:12> IPC3<2:0> IPC16<10:8> IPC7<10:8> IPC7<14:12> Interrupt Source ADC1 Conversion Done Comparator Event CRC Generator External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Change Notification Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter
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6.3 Interrupt Control and Status Registers
The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 6-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0<0>, the enable bit in IEC0<0> and the priority bits in the first position of IPC0 (IPC0<2:0>). Although they are not specifically part of the interrupt control hardware, two of the CPU control registers contain bits that control interrupt functionality. The CPU STATUS register (SR) contains the IPL2:IPL0 bits (SR<7:5>). These indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit, which together with IPL2:IPL0, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 6-1 through Register 6-30, in the following pages.
The PIC24FJ128GA010 family devices implement a total of 28 registers for the interrupt controller: * * * * * INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC14, and IPC16
Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a status bit which is set by the respective peripherals, or external signal, and is cleared via software. The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.
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REGISTER 6-1:
U-0 -- bit 15 R/W-0(1) IPL2 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(2,3)
SR: CPU STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DC(1) bit 8 R/W-0(1) IPL1(2,3) R/W-0(1) IPL0(2,3) R-0 RA(1) R/W-0 N(1) R/W-0 OV(1) R/W-0 Z(1) R/W-0 C(1) bit 0
IPL2:IPL0: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) See Register 2-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note 1: 2: 3:
REGISTER 6-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 3
CORCON: CORE CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- R/C-0 IPL3(2) R/W-0 PSV(1) U-0 -- U-0 -- bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less See Register 2-2 for the description of remaining bit(s) that are not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level.
Note 1: 2:
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REGISTER 6-3:
R/W-0 NSTDIS bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL U-0 -- bit 0
INTCON1: INTERRUPT CONTROL REGISTER 1
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled Unimplemented: Read as `0' MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as `0'
bit 14-5 bit 4
bit 3
bit 2
bit 1
bit 0
DS39747E-page 64
(c) 2009 Microchip Technology Inc.
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REGISTER 6-4:
R/W-0 ALTIVT bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT4EP R/W-0 INT3EP R/W-0 INT2EP R/W-0 INT1EP
INTCON2: INTERRUPT CONTROL REGISTER 2
R-0 DISI U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT0EP bit 0
ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI is not active Unimplemented: Read as `0' INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge
bit 14
bit 13-5 bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 6-5:
U-0 -- bit 15 R/W-0 T2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 -- R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 INT0IF bit 0
R/W-0 OC2IF
R/W-0 IC2IF
U-0 --
R/W-0 T1IF
R/W-0 OC1IF
R/W-0 IC1IF
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
DS39747E-page 66
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REGISTER 6-6:
R/W-0 U2TXIF bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF U-0 -- bit 8 R/W-0 SI2C1IF bit 0
U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-5 bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 6-7:
U-0 -- bit 15 R/W-0 IC5IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IF R/W-0 IC3IF U-0 -- U-0 -- U-0 -- R/W-0 SPI2IF
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0 -- R/W-0 PMPIF U-0 -- U-0 -- U-0 -- R/W-0 OC5IF U-0 -- bit 8 R/W-0 SPF2IF bit 0
Unimplemented: Read as `0' PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
bit 12-10 bit 9
bit 8 bit 7
bit 6
bit 5
bit 4-2 bit 1
bit 0
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REGISTER 6-8:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IF R/W-0 IC3IF U-0 -- U-0 -- R/W-0 SPI2IF R/W-0 SPI2IF U-0 -- bit 0
IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0 PMPIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0'
bit 13-7 bit 6
bit 5
bit 4-3 bit 2
bit 1
bit 0
(c) 2009 Microchip Technology Inc.
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REGISTER 6-9:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 CRCIF R/W-0 U2ERIF R/W-0 U1ERIF U-0 -- bit 0
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0'
bit 2
bit 1
bit 0
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REGISTER 6-10:
U-0 -- bit 15 R/W-0 T2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 -- R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 INT0IE bit 0
R/W-0 OC2IE
R/W-0 IC2IE
U-0 --
R/W-0 T1IE
R/W-0 OC1IE
R/W-0 IC1IE
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled
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REGISTER 6-11:
R/W-0 U2TXIE bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT1IE R/W-0 CNIE R/W-0 CMIE R/W-0 MI2C1IE
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0 R/W-0 INT2IE R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE U-0 -- bit 8 R/W-0 SI2C1IE bit 0
U2RXIE
U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-5 bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 6-12:
U-0 -- bit 15 R/W-0 IC5IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IE R/W-0 IC3IE U-0 -- U-0 -- U-0 -- R/W-0 SPI2IE
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 -- R/W-0 PMPIE U-0 -- U-0 -- U-0 -- R/W-0 OC5IE U-0 -- bit 8 R/W-0 SPF2IE bit 0
Unimplemented: Read as `0' PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled
bit 12-10 bit 9
bit 8 bit 7
bit 6
bit 5
bit 4-2 bit 1
bit 0
(c) 2009 Microchip Technology Inc.
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REGISTER 6-13:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IE R/W-0 INT3IE U-0 -- U-0 -- R/W-0 MI2C2IE R/W-0 SI2C2IE U-0 -- bit 0
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
R/W-0 RTCIE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT4IE: External Interrupt 4 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT3IE: External Interrupt 3 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0'
bit 13-7 bit 6
bit 5
bit 4-3 bit 2
bit 1
bit 0
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REGISTER 6-14:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 CRCIE R/W-0 U2ERIE R/W-0 U1ERIE U-0 -- bit 0
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0'
bit 2
bit 1
bit 0
(c) 2009 Microchip Technology Inc.
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REGISTER 6-15:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC1IP2 R/W-0 IC1IP1 R/W-0 IC1IP0 U-0 -- R/W-1 INT0IP2 R/W-0 INT0IP1
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
R/W-1 T1IP2 R/W-0 T1IP1 R/W-0 T1IP0 U-0 -- R/W-1 OC1IP2 R/W-0 OC1IP1 R/W-0 OC1IP0 bit 8 R/W-0 INT0IP0 bit 0
Unimplemented: Read as `0' T1IP2:T1IP0: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT0IP2:INT0IP0: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 6-16:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC2IP2 R/W-0 IC2IP1 R/W-0 IC2IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
R/W-1 T2IP2 R/W-0 T2IP1 R/W-0 T2IP0 U-0 -- R/W-1 OC2IP2 R/W-0 OC2IP1 R/W-0 OC2IP0 bit 8
Unimplemented: Read as `0' T2IP2:T2IP0: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
(c) 2009 Microchip Technology Inc.
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REGISTER 6-17:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SPF1IP2 R/W-0 SPF1IP1 R/W-0 SPF1IP0 U-0 -- R/W-1 T3IP2 R/W-0 T3IP1
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
R/W-1 R/W-0 U1RXIP1 R/W-0 U1RXIP0 U-0 -- R/W-1 SPI1IP2 R/W-0 SPI1IP1 R/W-0 SPI1IP0 bit 8 R/W-0 T3IP0 bit 0
U1RXIP2
Unimplemented: Read as `0' U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T3IP2:T3IP0: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 6-18:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 AD1IP2 R/W-0 AD1IP1 R/W-0 AD1IP0 U-0 -- R/W-1 U1TXIP2 R/W-0 U1TXIP1
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 U1TXIP0 bit 0
Unimplemented: Read as `0' AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 3 bit 2-0
(c) 2009 Microchip Technology Inc.
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REGISTER 6-19:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 MI2C1IP2 R/W-0 MI2C1IP1 R/W-0 MI2C1IP0 U-0 -- R/W-1 SI2C1IP2 R/W-0 SI2C1IP1
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
R/W-1 CNIP2 R/W-0 CNIP1 R/W-0 CNIP0 U-0 -- R/W-1 CMIP2 R/W-0 CMIP1 R/W-0 CMIP0 bit 8 R/W-0 SI2C1IP0 bit 0
Unimplemented: Read as `0' CNIP2:CNIP0: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' CMIP2:CMIP0: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C1IP2:MI2C1IP0: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C1IP2:SI2C1IP0: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 6-20:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 INT1IP2 R/W-0 INT1IP1
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT1IP0 bit 0
Unimplemented: Read as `0' INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
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REGISTER 6-21:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 OC3IP2 R/W-0 OC3IP1 R/W-0 OC3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
R/W-1 T4IP2 R/W-0 T4IP1 R/W-0 T4IP0 U-0 -- R/W-1 OC4IP2 R/W-0 OC4IP1 R/W-0 OC4IP0 bit 8
Unimplemented: Read as `0' T4IP2:T4IP0: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
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REGISTER 6-22:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT2IP2 R/W-0 INT2IP1 R/W-0 INT2IP0 U-0 -- R/W-1 T5IP2 R/W-0 T5IP1
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
R/W-1 R/W-0 U2TXIP1 R/W-0 U2TXIP0 U-0 -- R/W-1 U2RXIP2 R/W-0 U2RXIP1 R/W-0 U2RXIP0 bit 8 R/W-0 T5IP0 bit 0
U2TXIP2
Unimplemented: Read as `0' U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT2IP2:INT2IP0: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 6-23:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SPI2IP2 R/W-0 SPI2IP1 R/W-0 SPI2IP0 U-0 -- R/W-1 SPF2IP2 R/W-0 SPF2IP1
IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 SPF2IP0 bit 0
Unimplemented: Read as `0' SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 3 bit 2-0
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REGISTER 6-24:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC3IP2 R/W-0 IC3IP1 R/W-0 IC3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
R/W-1 IC5IP2 R/W-0 IC5IP1 R/W-0 IC5IP0 U-0 -- R/W-1 IC4IP2 R/W-0 IC4IP1 R/W-0 IC4IP0 bit 8
Unimplemented: Read as `0' IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
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REGISTER 6-25:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 OC5IP2 R/W-0 OC5IP1 R/W-0 OC5IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 3-0
REGISTER 6-26:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4
IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 R/W-0 PMPIP1 R/W-0 PMPIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
PMPIP2
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 3-0
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REGISTER 6-27:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SI2C2IP2 R/W-0 SI2C2IP1 R/W-0 SI2C2IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 MI2C2IP2 R/W-0 MI2C2IP1 R/W-0 MI2C2IP0 bit 8
Unimplemented: Read as `0' MI2C2IP2:MI2C2IP0: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C2IP2:SI2C2IP0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 7 bit 6-4
bit 3-0
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REGISTER 6-28:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT3IP2 R/W-0 INT3IP1 R/W-0 INT3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13
U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 INT4IP2 R/W-0 IN4IP1 R/W-0 INT4IP0 bit 8
Unimplemented: Read as `0' INT4IP2:INT4IP0: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT3IP2:INT3IP0: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 7 bit 6-4
bit 3-0
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REGISTER 6-29:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 RTCIP2 R/W-0 RTCIP1 R/W-0 RTCIP0 bit 8
Unimplemented: Read as `0' RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 7-0
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REGISTER 6-30:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U1ERIP2 R/W-0 U1ERIP1 R/W-0 U1ERIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
R/W-1 R/W-0 CRCIP1 R/W-0 CRCIP0 U-0 -- R/W-1 U2ERIP2 R/W-0 U2ERIP1 R/W-0 U2ERIP0 bit 8
CRCIP2
Unimplemented: Read as `0' CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11 bit 10-8
bit 7 bit 6-4
bit 3-0
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6.4
6.4.1
1. 2.
Interrupt Setup Procedures
INITIALIZATION
6.4.3
TRAP SERVICE ROUTINE
To configure an interrupt source: Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx Control register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: At a device Reset, the IPC registers are initialized, such that all user interrupt sources are assigned to priority level 4.
A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR.
6.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL.
To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction.
3.
4.
Clear the interrupt flag status bit associated with the peripheral in the associated IFSx Status register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx Control register.
6.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., `C' or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.
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NOTES:
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7.0
Note:
OSCILLATOR CONFIGURATION
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 6. "Oscillator" (DS39700) in the "PIC24F Family Reference Manual" for more information.
* On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources * Software-controllable switching between various clock sources * Software-controllable postscaler for selective clocking of CPU for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown A simplified diagram of the oscillator system is shown in Figure 7-1.
The oscillator system for PIC24FJ128GA010 family devices has the following features: * A total of four external and internal oscillator options as clock sources, providing 11 different clock modes
FIGURE 7-1:
PIC24FJ128GA010 FAMILY CLOCK DIAGRAM
Primary Oscillator
PIC24FJ128GA010 Family
XT, HS, EC CLKDIV<14:12> Postscaler
CLKO
OSC1
OSC2
8 MHz/ 4 MHz Postscaler
4 x PLL
XTPLL, HSPLL, ECPLL, FRCPLL
CPU
FRC Oscillator
FRCDIV
Peripherals
8 MHz (Nominal)
CLKDIV<10:8>
FRC
LPRC Oscillator
LPRC 31 kHz (Nominal)
Secondary Oscillator SOSCO SOSCEN Enable Oscillator SOSC
SOSCI
Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT Clock Source Option for Other Modules
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7.1 CPU Clocking Scheme
The system clock source can be provided by one of four sources: * Primary Oscillator (POSC) on the OSC1 and OSC2 pins * Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins * Fast Internal RC (FRC) Oscillator * Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSC2 I/O pin for some operating modes of the primary oscillator. settings are located in the Configuration registers in the program memory (refer to Section 23.1 "Configuration Bits" for further details.) The Primary Oscillator Configuration bits, POSCMD1:POSCMD0 (Configuration Word 2<1:0>), and the Initial Oscillator Select Configuration bits, FNOSC2:FNOSC0 (Configuration Word 2<10:8>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator with postscaler (FRCDIV) is the default (unprogrammed) selection. The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various clock modes, shown in Table 7-1.
7.2.1
CLOCK SWITCHING MODE CONFIGURATION BITS
The FCKSM Configuration bits (Configuration Word 2<7:6>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (`0'). The FSCM is enabled only when FCKSM1:FCKSM0 are both programmed (`00').
7.2
Oscillator Configuration
The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit
TABLE 7-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Primary Internal Internal POSCMD1: POSCMD0 11 xx 11 11 10 01 00 10 01 00 11 11 FNOSC2: FNOSC0 111 110 101 100 011 011 011 010 010 010 001 000 1 1 Note 1, 2 1 1 1
Oscillator Mode Fast RC Oscillator with Postscaler (FRCDIV) (Reserved) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (SOSC) Primary Oscillator (HS) with PLL Module (HSPLL) Primary Oscillator (XT) with PLL Module (XTPLL) Primary Oscillator (EC) with PLL Module (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL Module (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2:
OSC2 pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device.
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7.3 Control Registers
The operation of the oscillator is controlled by three Special Function Registers: * OSCCON * CLKDIV * OSCTUN The OSCCON register (Register 7-1) is the main control register for the oscillator. It controls clock source switching, and allows the monitoring of clock sources. The Clock Divider register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. The FRC Oscillator Tune register (Register 7-3) allows the user to fine tune the FRC oscillator over a range of approximately 12%. Each bit increment or decrement changes the factory calibrated frequency of the FRC oscillator by a fixed amount.
REGISTER 7-1:
U-0 -- bit 15 R/SO-0 CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12
OSCCON: OSCILLATOR CONTROL REGISTER
R-0 COSC2 R-0 COSC1 R-0 COSC0 U-0 -- R/W-x(1) NOSC2 R/W-x(1) NOSC1 R/W-x(1) NOSC0 bit 8 U-0 -- R-0(2) LOCK U-0 -- R/CO-0 CF U-0 -- R/W-0 SOSCEN R/W-0 OSWEN bit 0 CO = Clearable-Only bit W = Writable bit `1' = Bit is set SO = Settable-Only bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' COSC2:COSC0: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Unimplemented: Read as `0' NOSC2:NOSC0: New Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. Unimplemented: Read as `0' Reset values for these bits are determined by the FNOSC Configuration bits. Also resets to `0' during any valid clock switch, or whenever a non-PLL Clock mode is selected.
bit 11 bit 10-8
bit 7
bit 6 Note 1: 2:
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REGISTER 7-1:
bit 5
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
LOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled Unimplemented: Read as `0' CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected Unimplemented: Read as `0' SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete Reset values for these bits are determined by the FNOSC Configuration bits. Also resets to `0' during any valid clock switch, or whenever a non-PLL Clock mode is selected.
bit 4 bit 3
bit 2 bit 1
bit 0
Note 1: 2:
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REGISTER 7-2:
R/W-0 ROI bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 CO = Clearable-Only bit W = Writable bit `1' = Bit is set SO = Settable-Only bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0 DOZE2 R/W-0 DOZE1 R/W-0 DOZE0 R/W-0 DOZEN(1) R/W-0 RCDIV2 R/W-0 RCDIV1 R/W-1 RCDIV0 bit 8
ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 DOZEN: DOZE Enable bit(1) 1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio set to 1:1 RCDIV2:RCDIV0: FRC Postscaler Select bits 111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) Unimplemented: Read as `0' This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
bit 14-12
bit 11
bit 10-8
bit 7-0 Note 1:
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REGISTER 7-3:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 TUN0 bit 0
Unimplemented: Read as `0' TUN5:TUN0: FRC Oscillator Tuning bits 011111 = Maximum frequency deviation 011110 = * * * 000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 = * * * 100001 = 100000 = Minimum frequency deviation
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7.4 Clock Switching Operation
With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: Primary oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and CF (OSCCON<3>) status bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC status bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or SOSC (if SOSCEN remains set). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing sensitive code should not be executed during this time. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.
2.
3.
7.4.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit in the Flash Configuration Word 2 register must be programmed to `0'. (Refer to Section 23.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at `0' at all times.
4.
5.
6.
7.4.2
OSCILLATOR SWITCHING SEQUENCE
At a minimum, performing a clock switch requires this basic sequence: 1. If desired, read the COSC bits (OSCCON<14:12>), to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch.
2. 3.
4. 5.
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A recommended code sequence for a clock switch includes the following: 1. 2. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte, by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSC control bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON<7:0> in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is `0'. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine cause of failure.
EXAMPLE 7-1:
BASIC CODE SEQUENCE FOR CLOCK SWITCHING
3.
4.
5. 6. 7.
;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON, #0
8.
The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 7-1.
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8.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 10. PowerSaving Features" (DS39698) in the "PIC24F Family Reference Manual" for more information.
Note:
SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device.
8.2.1
SLEEP MODE
Sleep mode has these features: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. * The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. * The LPRC clock will continue to run in Sleep mode if the WDT is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of the these events: * On any interrupt source that is individually enabled * On any form of device Reset * On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered.
The PIC24FJ128GA010 family of devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: * * * * Clock Frequency Instruction-Based Sleep and Idle modes Software-Controlled Doze mode Selective Peripheral Control in Software
Combinations of these methods can be used to selectively tailor an application's power consumption, while still maintaining critical application features, such as timing sensitive communications.
8.1
Clock Frequency and Clock Switching
PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 7.0 "Oscillator Configuration".
8.2
Instruction-Based Power-Saving Modes
PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 8-1. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to "wake-up".
EXAMPLE 8-1:
PWRSAV PWRSAV
PWRSAV INSTRUCTION SYNTAX
; Put the device into SLEEP mode ; Put the device into IDLE mode
#SLEEP_MODE #IDLE_MODE
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8.2.2 IDLE MODE
Idle mode has these features: * The CPU will stop executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 "Selective Peripheral Module Control"). * If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: * Any interrupt that is individually enabled. * Any device Reset. * A WDT time-out. On wake-up from Idle, the clock is re-applied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR. It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation.
8.4
Selective Peripheral Module Control
Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked and thus consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: * The Peripheral Enable bit, generically named "XXXEN", located in the module's main control SFR. * The Peripheral Module Disable (PMD) bit, generically named "XXXMD", located in one of the PMD control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. Power consumption is reduced, but not by as much as the PMD bit does. Most peripheral modules have an enable bit; exceptions include Capture, Compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format "XXXIDL". By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.
8.2.3
INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode.
8.3
Doze Mode
Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE2:DOZE0 bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:256, with 1:1 being the default.
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9.0
Note:
I/O PORTS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 12. "I/O Ports with Peripheral Pin Select (PPS)" (DS39711) in the "PIC24F Family Reference Manual" for more information.
When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx), read the latch. Writes to the latch, write the latch. Reads from the port (PORTx), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. An example is the INT4 pin.
All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity.
9.1
Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a peripheral that shares the same pin. Figure 9-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected.
FIGURE 9-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data 1 0 1 0 Output Enable
Output Multiplexers
I/O
PIO Module
Read TRIS
Output Data
Data Bus WR TRIS
D CK
Q
I/O Pin
TRIS Latch D WR LAT + WR PORT CK Data Latch Q
Read LAT Input Data Read PORT
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9.1.1 OPEN-DRAIN CONFIGURATION
9.3
Input Change Notification
In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital-only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification.
The input change notification function of the I/O ports allows the PIC24FJ128GA010 family of devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature is capable of detecting input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 22 external signals (CN0 through CN21) that may be selected (enabled) for generating an interrupt request on a change-of-state. There are four control registers associated with the CN module. The CNEN1 and CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source that is connected to the pin, and eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups are enabled separately using the CNPU1 and CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. When the internal pull-up is selected, the pin uses VDDCORE as the pull-up source voltage. Make sure that there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output.
9.2
Configuring Analog Port Pins
The use of the AD1PCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications.
9.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be a NOP.
EXAMPLE 9-1:
MOV MOV NOP btss 0xFF00, W0 W0, TRISBB PORTB, #13
PORT WRITE/READ EXAMPLE
; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction
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10.0
Note:
TIMER1
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 14. "Timers" (DS39704) in the "PIC24F Family Reference Manual" for more information.
Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. 2. 3. 4. 5. 6. Set the TON bit (= 1). Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP2:T1IP0, to set the interrupt priority.
The Timer1 module is a 16-bit timer which can serve as the time counter for the Real-Time Clock, or operate as a free-running interval timer/counter. Timer1 can operate in three modes: * 16-Bit Timer * 16-Bit Synchronous Counter * 16-Bit Asynchronous Counter Timer1 also supports these features: * Timer gate operation * Selectable prescaler settings * Timer operation during CPU Idle and Sleep modes * Interrupt on 16-bit Period register match or falling edge of external gate signal
FIGURE 10-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS1:TCKPS0
SOSCO/ T1CK SOSCEN SOSCI Gate Sync TCY TGATE 1 0 Reset
1x 01 00
TON
2 Prescaler 1, 8, 64, 256
TGATE TCS Q Q D CK 0 TMR1 1 Comparator TSYNC Sync
Set T1IF
Equal
PR1
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REGISTER 10-1:
R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0
T1CON: TIMER1 CONTROL REGISTER
U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit 1 = External clock from pin T1CK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0'
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3 bit 2
bit 1
bit 0
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11.0
Note:
TIMER2/3 AND TIMER4/5
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 14. "Timers" (DS39704) in the "PIC24F Family Reference Manual" for more information.
To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. 4. Set the T32 bit (T2CON<3> or T4CON<3> = 1). Select the prescaler ratio for Timer2 or Timer4 using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value. PR3 (or PR5) will contain the most significant word of the value, while PR2 (or PR4) contains the least significant word. If interrupts are required, set the interrupt enable bit, T3IE or T5IE; use the priority bits, T3IP2:T3IP0 or T5IP2:T5IP0, to set the interrupt priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. Set the TON bit (= 1).
The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. As a 32-bit timer, Timer2/3 and Timer4/5 operate in three modes: * Two independent 16-bit timers (Timer2 and Timer3) with all 16-bit operating modes * Single 32-bit Timer * Single 32-bit Synchronous Counter They also support these features: * * * * * Timer gate operation Selectable prescaler settings Timer operation during Idle and Sleep modes Interrupt on a 32-bit Period register match ADC Event Trigger (Timer4/5 only)
5.
6.
The timer value at any point is stored in the register pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5) always contains the most significant word of the count, while TMR2 (TMR4) contains the least significant word. To configure any of the timers for individual 16-bit operation: 1. Clear the T32 bit corresponding to that timer (T2CON<3> for Timer2 and Timer3 or T4CON<3> for Timer4 and Timer5). Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE; use the priority bits, TxIP2:TxIP0, to set the interrupt priority. Set the TON bit (TxCON<15> = 1).
Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the ADC Event Trigger; this is implemented only with Timer5. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON and T5CON registers. T2CON and T4CON are shown in generic form in Register 11-1; T3CON and T5CON are shown in Register 11-2. For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word; Timer3 and Timer4 are the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.
2. 3. 4. 5.
6.
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FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256
T2CK (T4CK) Gate Sync TCY TGATE
1x 01 00
TON
TGATE TCS
Set T3IF (T5IF)
1 0 PR3 (PR5)
Q Q
D CK PR2 (PR4)
ADC Event Trigger*
Equal MSB Reset 16
Comparator LSB TMR3 (TMR5) TMR2 (TMR4) Sync
Read TMR2 (TMR4) Write TMR2 (TMR4) 16 TMR3HLD (TMR5HLD) 16
Data Bus<15:0> Note: * The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. The ADC Event Trigger is available only on Timer4/5.
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FIGURE 11-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256
T2CK (T4CK) Gate Sync TGATE TCY 1 Set T2IF (T4IF) 0 Reset Q Q D CK
1x 01 00
TCS TGATE
TMR2 (TMR4)
Sync
Equal
Comparator
PR2 (PR4)
FIGURE 11-3:
TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256
T3CK (T5CK)
Sync
1x 01
TGATE TCY 1 Set T3IF (T5IF) 0 Reset Q Q D CK
00 TCS TGATE
TMR3 (TMR5)
ADC Event Trigger* Equal
Comparator
PR3 (PR5) * The ADC Event Trigger is available only on Timer4/5.
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REGISTER 11-1:
R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 R/W-0 T32(1) U-0 -- R/W-0 TCS U-0 -- bit 0
TxCON: TIMER2 AND TIMER4 CONTROL REGISTER
U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON<3> = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS1:TCKPS0: Timer2 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 T32: 32-Bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers Unimplemented: Read as `0' TCS: Timerx Clock Source Select bit 1 = External clock from pin TxCK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3
bit 2 bit 1
bit 0 Note 1:
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REGISTER 11-2:
R/W-0 TON(1) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE
(1)
TyCON: TIMER3 AND TIMER5 CONTROL REGISTER
U-0 -- R/W-0 TSIDL
(1)
U-0 --
U-0 --
U-0 --
U-0 --
U-0 -- bit 8
R/W-0 TCKPS1
(1)
R/W-0 TCKPS0
(1)
U-0 --
U-0 --
R/W-0 TCS
(1)
U-0 -- bit 0
TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TCS: Timery Clock Source Select bit(1) 1 = External clock from pin TyCK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON.
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3-2 bit 1
bit 0 Note 1:
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NOTES:
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12.0
Note:
INPUT CAPTURE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 15. "Input Capture" (DS39701) in the "PIC24F Family Reference Manual" for more information.
* Capture timer value on every fourth rising edge of input applied at the ICx pin * Capture timer value on every 16th rising edge of input applied at the ICx pin * Capture timer value on every rising and every falling edge of input applied at the ICx pin * Device wake-up from capture pin during CPU Sleep and Idle modes The input capture module has a four-level FIFO buffer. The number of capture events required to generate a CPU interrupt can be selected by the user.
The input capture module has multiple operating modes which are selected via the ICxCON register. The operating modes include: * Capture timer value on every falling edge of input applied at the ICx pin * Capture timer value on every rising edge of input applied at the ICx pin
FIGURE 12-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-Bit Timers TMRy TMRx
16
16
1 Prescaler Counter (1, 4, 16) ICx pin 3 Edge Detection Logic and Clock Synchronizer ICM<2:0> (ICxCON<2:0>) Mode Select ICOV, ICBNE (ICxCON<4:3>) FIFO R/W Logic
0
ICTMR (ICxCON<7>)
ICxBUF ICI<1:0> ICxCON Interrupt Logic
System Bus
Set Flag ICxIF (in IFSx Register)
Note: An `x' in a signal, register or bit name denotes the number of the capture channel.
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FIFO
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12.1 Input Capture Registers
ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0 -- R/W-0 ICSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ICI1 R/W-0 ICI0 R-0, HC ICOV R/W-0, HC ICBNE R/W-0 ICM2 R/W-0 ICM1 R/W-0 ICM0 bit 0 HC = Hardware Clearable W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 12-1:
U-0 -- bit 15 R/W-0 ICTMR bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
(1)
Unimplemented: Read as `0' ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module will halt in CPU Idle mode 0 = Input capture module will continue to operate in CPU Idle mode Unimplemented: Read as `0' ICTMR: Input Capture x Timer Select bit(1) 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event ICI1:ICI0: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM2:ICM0: Input Capture x Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) - ICI<1:0> does not control interrupt generation for this mode 000 = Input capture module turned off Timer selections may vary. Refer to the device data sheet for details.
bit 12-8 bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
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13.0
Note:
OUTPUT COMPARE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 16. "Output Compare" (DS39706) in the "PIC24F Family Reference Manual" for more information.
FIGURE 13-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1) OCxRS(1)
OCxR(1)
Output Logic 3
SQ R Output Enable
OCx(1)
Comparator 0 16 1 16 OCTSEL 0 1
OCM2:OCM0 Mode Select
OCFA or OCFB(2)
TMR register inputs from time bases (see Note 3).
Period match signals from time bases (see Note 3).
Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5. 3: Each output compare channel can use either Timer2 or Timer3.
13.1
MODES OF OPERATION
13.2
Each output compare module has the following modes of operation: * Single Compare Match mode * Dual Compare Match mode generating: - Single Output Pulse mode - Continuous Output Pulse mode * Simple Pulse-Width Modulation mode: - with Fault protection input - without Fault protection input
Setup for Single Output Pulse Generation
When the OCM control bits (OCxCON<2:0>) are set to `100', the selected output compare channel initializes the OCx pin to the low state and generates a single output pulse.
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To generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate time to the rising edge of the output pulse relative to the TMRy start value (0000h). 3. Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. Write the values computed in steps 2 and 3 above into the Compare register, OCxR, and the Secondary Compare register, OCxRS, respectively. 5. Set the Timer Period register, PRy, to value equal to or greater than value in OCxRS, the Secondary Compare register. 6. Set the OCM bits to `100' and the OCTSEL (OCxCON<3>) bit to the desired timer source. The OCx pin state will now be driven low. 7. Set the TON (TyCON<15>) bit to `1' which enables the compare time base to count. 8. Upon the first match between TMRy and OCxR, the OCx pin will be driven high. 9. When the incrementing timer, TMRy, matches the Secondary Compare register, OCxRS, the second and trailing edge (high-to-low) of the pulse is driven onto the OCx pin. No additional pulses are driven onto the OCx pin and it remains at low. As a result of the second compare match event, the OCxIF interrupt flag bit is set which will result in an interrupt, if it is enabled, by setting the OCxIE bit. For further information on peripheral interrupts, refer to Section 6.0 "Interrupt Controller". 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to `100'. Disabling and re-enabling of the timer and clearing the TMRy register are not required, but may be advantageous for defining a pulse from a known event time boundary. The output compare module does not have to be disabled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OCxCON register. 1.
13.3
Setup for Continuous Output Pulse Generation
When the OCM control bits (OCxCON<2:0>) are set to `101', the selected output compare channel initializes the OCx pin to the low state and generates output pulses on each and every compare match event. For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate time to the rising edge of the output pulse relative to the TMRy start value (0000h). 3. Calculate the time to the falling edge of the pulse, based on the desired pulse width and the time to the rising edge of the pulse. 4. Write the values computed in step 2 and 3 above into the Compare register, OCxR, and the Secondary Compare register, OCxRS, respectively. 5. Set Timer Period register, PRy, to value equal to or greater than value in OCxRS, the Secondary Compare register. 6. Set the OCM bits to `101' and the OCTSEL bit to the desired timer source. The OCx pin state will now be driven low. 7. Enable the compare time base by setting the TON (TyCON<15>) bit to `1'. 8. Upon the first match between TMRy and OCxR, the OCx pin will be driven high. 9. When the compare time base, TMRy, matches the Secondary Compare register, OCxRS, the second and trailing edge (high-to-low) of the pulse is driven onto the OCx pin. 10. As a result of the second compare match event, the OCxIF interrupt flag bit set. 11. When the compare time base and the value in its respective Period register match, the TMRy register resets to 0x0000 and resumes counting. 12. Steps 8 through 11 are repeated and a continuous stream of pulses is generated, indefinitely. The OCxIF flag is set on each OCxRS-TMRy compare match event. 1.
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13.4 Pulse-Width Modulation Mode
EQUATION 13-1:
The following steps should be taken when configuring the output compare module for PWM operation: 1. 2. 3. 4. Set the PWM period by writing to the selected Timer Period register (PRy). Set the PWM duty cycle by writing to the OCxRS register. Write the OCxR register with the initial duty cycle. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. Configure the output compare module for one of two PWM operation modes by writing to the Output Compare mode bits OCM<2:0> (OCxCON<2:0>). Set the TMRy prescale value and enable the time base by setting TON (TxCON<15>) = 1. Note: The OCxR register should be initialized before the output compare module is first enabled. The OCxR register becomes a Read-Only Duty Cycle register when the module is operated in the PWM modes. The value held in OCxR will become the PWM duty cycle for the first PWM period. The contents of the Duty Cycle Buffer register, OCxRS, will not be transferred into OCxR until a time base period match occurs.
CALCULATING THE PWM PERIOD(1)
PWM Period = [(PRy) + 1] * TCY * (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note 1: Based on TCY = TOSC * 2, Doze mode and PLL are disabled. Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles.
5.
13.4.2
PWM DUTY CYCLE
6.
The PWM duty cycle is specified by writing to the OCxRS register. The OCxRS register can be written to at any time, but the duty cycle value is not latched into OCxR until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. In the PWM mode, OCxR is a read-only register. Some important boundary parameters of the PWM duty cycle include: * If the Duty Cycle register, OCxR, is loaded with 0000h, the OCx pin will remain low (0% duty cycle). * If OCxR is greater than PRy (Timer Period register), the pin will remain high (100% duty cycle). * If OCxR is equal to PRy, the OCx pin will be low for one time base count value and high for all other count values. See Example 13-1 for PWM mode timing details. Table 13-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS.
13.4.1
PWM PERIOD
The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation 13-1.
EQUATION 13-2:
CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
log10 Maximum PWM Resolution (bits) = FCY (FPWM * (Timer Prescale Value)) bits log10(2)
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
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EXAMPLE 13-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
1. Find the Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2/FOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) * TCY * (Timer 2 Prescale Value) 19.2 s = (PR2 + 1) * 62.5 ns * 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate: PWM Resolution = log10 (FCY/FPWM)/log102) bits = (log10 (16 MHz/52.08 kHz)/log102) bits = 8.3 bits Note 1: Based on TCY = TOSC * 2, Doze mode and PLL are disabled.
TABLE 13-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
7.6 Hz 8 FFFFh 16 61 Hz 1 FFFFh 16 122 Hz 1 7FFFh 15 977 Hz 1 0FFFh 12 3.9 kHz 1 03FFh 10 31.3 kHz 1 007Fh 7 125 kHz 1 001Fh 5
PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1:
Based on TCY = TOSC * 2, Doze mode and PLL are disabled.
TABLE 13-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHZ)(1)
30.5 Hz 8 FFFFh 16 244 Hz 1 FFFFh 16 488 Hz 1 7FFFh 15 3.9 kHz 1 0FFFh 12 15.6 kHz 1 03FFh 10 125 kHz 1 007Fh 7 500 kHz 1 001Fh 5
PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1:
Based on TCY = TOSC * 2; Doze mode and PLL are disabled.
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REGISTER 13-1:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R-0, HC OCFLT R/W-0 OCTSEL
(1)
OCxCON: OUTPUT COMPARE x CONTROL REGISTER
U-0 -- R/W-0 OCSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 OCM2 R/W-0 OCM1 R/W-0 OCM0 bit 0
Unimplemented: Read as `0' OCSIDL: Stop Output Compare x Module Stop in Idle Control bit 1 = Output capture x will halt in CPU Idle mode 0 = Output capture x will continue to operate in CPU Idle mode Unimplemented: Read as `0' OCFLT: PWM Fault Condition Status bit(1) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) OCTSEL: Output Compare x Timer Select bit(1) 1 = Timer3 is the clock source for output Compare x 0 = Timer2 is the clock source for output Compare x OCM2:OCM0: Output Compare x Mode Select bits 111 = PWM mode on OCx, Fault pin enabled(2) 110 = PWM mode on OCx, Fault pin disabled(2) 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled Refer to the device data sheet for specific time bases available to the output compare module. OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.
bit 12-5 bit 4
bit 3
bit 2-0
Note 1: 2:
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14.0
Note:
SERIAL PERIPHERAL INTERFACE (SPI)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 23. "Serial Peripheral Interface (SPI)" (DS39699) in the PIC24F Family Reference Manual for more information.
To set up the SPI module for the Standard Master mode of operation: 1. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register to set the interrupt priority. Write the desired settings to the SPIxCON register with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register.
The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with Motorola's SPI and SIOP interfaces. The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer. In Enhanced Buffer mode, data is shifted through an 8-level FIFO buffer. Note: Do not perform read-modify-write operations (such as bit-oriented instructions) on the SPIxBUF register, in either Standard or Enhanced Buffer mode.
2. 3. 4. 5.
To set up the SPI module for the Standard Slave mode of operation: 1. 2. Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit (SPIxCON1<7>) must be set to enable the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>).
The module also supports a basic framed SPI protocol while operating in either Master or Slave modes. A total of four framed SPI configurations are supported. The SPI serial interface consists of four pins: * * * * SDIx: Serial Data Input SDOx: Serial Data Output SCKx: Shift Clock Input or Output SSx: Active-Low Slave Select or Frame Synchronization I/O Pulse 3.
4. 5.
The SPI module can be configured to operate, using 2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used. A block diagram of the module is shown in Figure 14-1 and Figure 14-2. Note: In this section, the SPI modules are referred to together as SPIx or separately as SPI1 and SPI2. Special Function Registers will follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 or SPI2 module.
6. 7.
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To set up the SPI module for the Enhanced Buffer Master mode of operation: 1. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 2. Clear the SPIxBUF register. If using interrupts: * Clear the SPIxIF bit in the respective IFSx register. * Set the SPIxIE bit in the respective IECx register. * Write the SPIxIP bits in the respective IPCx register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>).
2.
3.
3. 4. 5. 6.
4. 5. 6. 7. 8.
FIGURE 14-1:
SCKx
SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler
FCY
SSx/FSYNCx
SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock
SDOx SDIx bit 0
SPIxSR
Transfer
Transfer
SPIxBUF
Read SPIxBUF
Write SPIxBUF 16 Internal Data Bus
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FIGURE 14-2:
SCKx
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler FCY
SSx/FSYNCx
SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock
SDOx SDIx bit0
SPIxSR
Transfer
Transfer
8-Level FIFO Receive Buffer
8-Level FIFO Transmit Buffer
SPIxBUF
Read SPIxBUF
Write SPIxBUF 16 Internal Data Bus
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REGISTER 14-1:
R/W-0 SPIEN bit 15 R/W-0 SRMPT bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 SPIROV R/W-0 SRXMPT R/W-0 SISEL2 R/W-0 SISEL1 R/W-0 SISEL0 R-0 SPITBF R-0 SPIREF bit 0
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
U-0 -- R/W-0 SPISIDL U-0 -- U-0 -- R-0 SPIBEC2 R-0 SPIBEC1 R-0 SPIBEC0 bit 8
SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module Unimplemented: Read as `0' SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and ready to send or receive 0 = SPIx Shift register is not emptyRead as `0' SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty' SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when last bit is shifted into SPIxSR, as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot 011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set) 010 = Interrupt when SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read, as a result, the buffer is empty (SRXMPT bit set)
bit 14 bit 13
bit 12-11 bit 10-8
bit 7
bit 6
bit 5
bit 4-2
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REGISTER 14-1:
bit 1
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. In Enhanced Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty In Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.
bit 0
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REGISTER 14-2:
U-0 -- bit 15 R/W-0 SSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12
SPIXCON1: SPIx CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 PPRE0 bit 0
R/W-0 CKP
R/W-0 MSTEN
R/W-0 SPRE2
R/W-0 SPRE1
R/W-0 SPRE0
R/W-0 PPRE1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
Unimplemented: Read as `0' DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used by module. Pin controlled by port function. CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode SPRE2:SPRE0: Secondary Prescale (Master mode) bits 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 PPRE1:PPRE0: Primary Prescale (Master mode) bits 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1
The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1).
Note 1:
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REGISTER 14-3:
R/W-0 FRMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 SPIFPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SPIFE R/W-0 SPIBEN bit 0
R/W-0 SPIFSD
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14
bit 13
bit 12-2 bit 1
bit 0
FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled 0 = Framed SPIx support disabled SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as `0' SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode)
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FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave)
SDOx
SDIx
Serial Receive Buffer (SPIxRXB)
Serial Receive Buffer (SPIxRXB)
Shift Register (SPIxSR) MSb LSb
SDIx
SDOx MSb
Shift Register (SPIxSR) LSb
Serial Transmit Buffer (SPIxTXB)
Serial Transmit Buffer (SPIxTXB)
SPIx Buffer (SPIxBUF)
SCKx
Serial Clock
SCKx
SPIx Buffer (SPIxBUF)
SSx (MSTEN (SPIxCON1<5> = 1)) Note 1: 2: (SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0)
Using the SSx pin in the Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF.
FIGURE 14-4:
SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
PROCESSOR 2 (SPI Enhanced Buffer Slave)
SDIx
PROCESSOR 1 (SPI Enhanced Buffer Master)
SDOx
Shift Register (SPIxSR) MSb LSb
SDIx
SDOx
Shift Register (SPIxSR) MSb LSb
8-Level FIFO Buffer
8-Level FIFO Buffer
SPIx Buffer (SPIxBUF)
SCKx
Serial Clock
SCKx
SPIx Buffer (SPIxBUF)
SSx
SSx
MSTEN (SPIxCON1<5> = 1 and SPIBEN (SPIxCON2<0>) = 1 Note 1: 2:
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 and SPIBEN (SPIxCON2<0>) = 1
Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF.
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FIGURE 14-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F (SPI Slave, Frame Slave) SDOx SDIx PROCESSOR 2
SDIx SCKx SSx Serial Clock
SDOx SCKx SSx
Frame Sync Pulse
FIGURE 14-6:
SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F SPI Master, Frame Slave) SDOx SDIx SCKx SSx Serial Clock SDIx SDOx SCKx SSx PROCESSOR 2
Frame Sync Pulse
FIGURE 14-7:
SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F (SPI Slave, Frame Slave) SDOx SDIx PROCESSOR 2
SDIx SCKx SSx Serial Clock
SDOx SCKx SSx
Frame Sync. Pulse
FIGURE 14-8:
SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F (SPI Master, Frame Slave) SDOx SDIx PROCESSOR 2
SDIx SCKx SSx Serial Clock
SDOx SCKx SSx
Frame Sync Pulse
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EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)
FSCK = FCY Primary Prescaler * Secondary Prescaler
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 14-1:
SAMPLE SCK FREQUENCIES(1,2)
FCY = 16 MHz Secondary Prescaler Settings 1:1 1:1 4:1 16:1 64:1 FCY = 5 MHz Invalid 4000 1000 250 2:1 8000 2000 500 125 4:1 4000 1000 250 63 6:1 2667 667 167 42 8:1 2000 500 125 31
Primary Prescaler Settings
Primary Prescaler Settings
1:1 4:1 16:1 64:1
5000 1250 313 78
2500 625 156 39
1250 313 78 20
833 208 52 13
625 156 39 10
Note 1: 2:
Based on FCY = FOSC/2, Doze mode and PLL are disabled. SCKx frequencies shown in kHz.
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15.0
Note:
INTER-INTEGRATED CIRCUIT (I2CTM)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 24. "InterIntegrated CircuitTM (I2CTM)" (DS39702) in the "PIC24F Family Reference Manual" for more information.
15.1
Communicating as a Master in a Single Master Environment
The details of sending a message in Master mode depends on the communications protocol for the device being communicated with. Typically, the sequence of events is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Assert a Start condition on SDAx and SCLx. Send the I 2C device address byte to the slave with a write indication. Wait for and verify an Acknowledge from the slave. Send the first data byte (sometimes known as the command) to the slave. Wait for and verify an Acknowledge from the slave. Send the serial memory address low byte to the slave. Repeat steps 4 and 5 until all data bytes are sent. Assert a Repeated Start condition on SDAx and SCLx. Send the device address byte to the slave with a read indication. Wait for and verify an Acknowledge from the slave. Enable master reception to receive serial memory data. Generate an ACK or NACK condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx.
The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, A/D Converters, etc. The I C module supports these features: * * * * * * * * * Independent master and slave logic 7-bit and 10-bit device addresses General call address, as defined in the I2C protocol Clock stretching to provide delays for the processor to respond to a slave data request Both 100 kHz and 400 kHz bus specifications. Configurable address masking Multi-Master modes to prevent loss of messages in arbitration Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address Automatic SCL
2
A block diagram of the module is shown in Figure 15-1.
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FIGURE 15-1: I2CTM BLOCK DIAGRAM
Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSB SDAx Address Match
Read
SCLx
Match Detect
Write I2CxMSK Write Read
I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic
Write I2CxSTAT Read Write I2CxCON Read
Collision Detect
Acknowledge Generation Clock Stretching
Write
I2CxTRN LSB Shift Clock Reload Control Read
Write I2CxBRG Read
BRG Down Counter
TCY/2
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15.2 Setting Baud Rate When Operating as a Bus Master 15.3 Slave Address Masking
The I2CxMSK register (Register 15-3) designates address bit positions as "don't care" for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond, whether the corresponding address bit value is a `0' or `1'. For example, when I2CxMSK is set to `00100000', the slave module will detect both addresses `0000000' and `00100000'. To enable address masking, the IPMI (Intelligent Peripheral Management Interface) must be disabled by clearing the IPMIEN bit (I2CxCON<11>).
To compute the Baud Rate Generator reload value, use the following equation:
EQUATION 15-1:(1)
I2CxBRG = (FCY/FSCL - FCY/10,000,000) - 1 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
TABLE 15-1:
Required System FSCL 100 kHz 100 kHz 100 kHz 400 kHz 400 kHz 400 kHz 400 kHz 1 MHz 1 MHz 1 MHz Legend: Note 1: 2: 3: 4:
I2CTM CLOCK RATES(1,3,4)
I2CxBRG Value FCY 16 MHz 8 MHz 4 MHz 16 MHz 8 MHz 4 MHz 2 MHz 16 MHz 8 MHz 4 MHz (Decimal) 157 78 39 37 18 9 4 13 6 3 (Hexadecimal) 9D 4E 27 25 12 9 4 D 6 3 Actual FSCL 100 kHz 100 kHz 99 kHz 404 kHz 404 kHz 385 kHz(2) 385 kHz(2) 1,026 KHz 1,026 KHz 909 KHz
Shaded rows represent invalid reload values for a given FSCL and FCY. Based on TCY = TOSC * 2(2), Doze mode and PLL are disabled. This is the closest value to 400 kHz for this value of FCY. FCY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz. I2CxBRG cannot have a value of less than 2. Address masking does not affect behavior. Refer to Table 15-2 for a summary of these reserved addresses .
(1)
As a result of changes in the I2C protocol, several I2C addresses are reserved and will not be acknowledged in Slave mode.
TABLE 15-2:
RESERVED I CTM ADDRESSES
R/W Bit 0 1 x x x x x x
2
Slave Address 0000 000 0000 000 0000 001 0000 010 0000 011 0000 1xx 1111 1xx 1111 0xx Note 1: 2: 3:
Description General Call Address(2) Start Byte CBUS Address Reserved Reserved HS Mode Master Code Reserved 10-Bit Slave Upper Byte(3)
The above address bits will not cause an address match, independent of address mask settings. Address will be Acknowledged only if GCEN = 1. Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 15-1:
R/W-0 I2CEN bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 STREN R/W-0 ACKDT R/W-0, HC ACKEN R/W-0, HC RCEN R/W-0, HC PEN R/W-0, HC RSEN
I2CxCON: I2Cx CONTROL REGISTER
U-0 -- R/W-0 I2CSIDL R/W-1, HC SCLREL R/W-0 IPMIEN R/W-0 A10M R/W-0 DISSLW R/W-0 SMEN bit 8 R/W-0, HC SEN bit 0
I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module. All I2C pins are controlled by port functions. Unimplemented: Read as `0' I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write `1' to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
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REGISTER 15-1:
bit 5
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enabled bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enabled bit (when operating as I2C master) 1 = Initiate Start condition on SDA and SCL pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 15-2:
R-0, HSC ACKSTAT bit 15 R/C-0, HSC IWCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0, HSC I2COV R-0, HSC D/A R/C-0, HSC R/C-0, HSC P S R-0, HSC R/W R-0, HSC RBF
I2CxSTAT: I2Cx STATUS REGISTER
U-0 -- U-0 -- U-0 -- R/C-0, HSC BCL R-0, HSC GCSTAT R-0, HSC ADD10 bit 8 R-0, HSC TBF bit 0
R-0, HSC TRSTAT
ACKSTAT: Acknowledge Status bit 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. TRSTAT: Transmit Status bit (When operating as I2C master. Applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte. P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
bit 14
bit 13-11 bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
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REGISTER 15-2:
bit 3
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R/W: Read/Write bit Information (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV written with received byte. Hardware clear when software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
bit 2
bit 1
bit 0
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REGISTER 15-3:
U-0 -- bit 15 R/W-0 AMSK7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 AMSK6 R/W-0 AMSK5 R/W-0 AMSK4 R/W-0 AMSK3 R/W-0 AMSK2 R/W-0 AMSK1
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AMSK9 R/W-0 AMSK8 bit 8 R/W-0 AMSK0 bit 0
Unimplemented: Read as `0' AMSK9:AMSK0: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position
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16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 21. "UART" (DS39708) in the "PIC24F Family Reference Manual" for more information. * Fully Integrated Baud Rate Generator with 16-Bit Prescaler * Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS * 4-Deep First-In-First-Out (FIFO) Transmit Data Buffer * 4-Deep, FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Supports Automatic Baud Rate Detection * IrDA Encoder and Decoder Logic * 16x Baud Clock Output for IrDA Support A simplified block diagram of the UART is shown in Figure 16-1. The UART module consists of these key important hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver
Note:
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA encoder and decoder. The primary features of the UART module are: * Full-Duplex, 8 or 9-Bit Data Transmission through the UxTX and UxRX pins * Even, Odd or No Parity Options (for 8-bit data) * One or Two Stop bits * Hardware Flow Control Option with UxCTS and UxRTS pins
FIGURE 16-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA(R)
BCLKx
Hardware Flow Control
UxRTS UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
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16.1 UART Baud Rate Generator (BRG)
The UART module includes a dedicated 16-bit Baud Rate Generator. The BRGx register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. The maximum baud rate (BRGH = 0) possible is FCY/16 (for BRGx = 0), and the minimum baud rate possible is FCY/(16 * 65536). Equation 16-2 shows the formula for computation of the baud rate with BRGH = 1.
EQUATION 16-2:
EQUATION 16-1:
UART BAUD RATE WITH BRGH = 0(1)
FCY 16 * (BRGx + 1) FCY -1 16 * Baud Rate
UART BAUD RATE WITH BRGH = 1(1)
FCY 4 * (BRGx + 1) FCY 4 * Baud Rate -1
Baud Rate =
Baud Rate =
BRGx = Note 1:
BRGx = Note 1:
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
Example 16-1 shows the calculation of the baud rate error for the following conditions: * FCY = 4 MHz * Desired Baud Rate = 9600
The maximum baud rate (BRGH = 1) possible is FCY/4 (for BRGx = 0) and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the BRGx register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate.
EXAMPLE 16-1:
Desired Baud Rate BRGx BRGx BRGx Solving for BRGx value:
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
= FCY/(16 (BRGx + 1)) = ((FCY/Desired Baud Rate)/16) - 1 = ((4000000/9600)/16) - 1 = 25
Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600)/9600 = 0.16%
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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16.2
1.
Transmitting in 8-Bit Data Mode
16.5
1. 2. 3.
2. 3. 4.
5.
6.
Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the BRGx register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write data byte to lower byte of TXxREG word. The value will be immediately transferred to the Transmit Shift Register (TSR), and the serial bit stream will start shifting out with next rising edge of the baud clock. Alternately, the data byte may be transferred while UTXEN = 0, and then the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bit, UTXISELx.
Receiving in 8-Bit or 9-Bit Data Mode
4.
5.
Set up the UART (as described in Section 16.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, URXISELx. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read UxRXREG.
The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values.
16.6
Operation of UxCTS and UxRTS Control Pins
16.3
1. 2. 3. 4. 5.
Transmitting in 9-Bit Data Mode
6.
Set up the UART (as described in Section 16.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write UxTXREG as a 16-bit value only. A word write to UxTXREG triggers the transfer of the 9-bit data to the TSR. Serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bit, UTXISELx.
UARTx Clear to Send (UxCTS) and Request to Send (UxRTS) are the two hardware controlled pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE register configure these pins.
16.7
Infrared Support
The UART module provides two types of infrared UART support: one is the IrDA clock output to support external IrDA encoder and decoder device (legacy module support) and the other is the full implementation of the IrDA encoder and decoder.
16.8
16.4
Break and Sync Transmit Sequence
External IrDA Support - IrDA Clock Output
The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. 1. 2. 3. 4. 5. Configure the UART for the desired mode. Set UTXEN and UTXBRK - sets up the Break character, Load the UxTXREG with a dummy character to initiate transmission (value is ignored). Write `55h' to UxTXREG - loads Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits.
To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. With UEN<1:0> = 11, the BCLKx pin will output the 16x baud clock if the UART module is enabled. It can be used to support the IrDA codec chip.
16.9
Built-in IrDA Encoder and Decoder
The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit UxMODE<12>. When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter.
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REGISTER 16-1:
R/W-0 UARTEN bit 15 R/W-0, HC WAKE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 LPBACK R/W-0, HC ABAUD R/W-0 RXINV R/W-0 BRGH R/W-0 PDSEL1 R/W-0 PDSEL0 U-0 --
UxMODE: UARTx MODE REGISTER
R/W-0 USIDL R/W-0 IREN(1) R/W-0 RTSMD U-0 -- R/W-0 UEN1 R/W-0 UEN0 bit 8 R/W-0 STSEL bit 0
UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal Unimplemented: Read as `0' USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode IREN: IrDA Encoder and Decoder Enable bit(1) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode Unimplemented: Read as `0' UEN1:UEN0: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latches WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = No wake-up enabled LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode) This feature is only available for the 16x BRG mode (BRGH = 0).
bit 14 bit 13
bit 12
bit 11
bit 10 bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
Note 1:
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REGISTER 16-1:
bit 2-1
UxMODE: UARTx MODE REGISTER (CONTINUED)
PDSEL1:PDSEL0: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is only available for the 16x BRG mode (BRGH = 0).
bit 0
Note 1:
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REGISTER 16-2:
R/W-0 UTXISEL1 bit 15 R/W-0 URXISEL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15,13 C = Clearable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 URXISEL0 R/W-0 ADDEN R-1 RIDLE R-0 PERR R-0 FERR R/C-0 OERR R-0 URXDA bit 0
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 UTXISEL0 U-0 -- R/W-0, HC UTXBRK R/W-0 UTXEN R-0 UTXBF R-1 TRMT bit 8
R/W-0 TXINV
UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) TXINV: Transmit Polarity Inversion bit IREN = 0: 1 = TX Idle state is `0' 0 = TX Idle state is `1' IREN = 1: 1 = IrDA encoded TX Idle state is `1' 0 = IrDA encoded TX Idle state is `0' Unimplemented: Read as `0' UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed UTXEN: Transmit Enable bit 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits 11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled
bit 14
bit 12 bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5
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REGISTER 16-2:
bit 4
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the RSR to the empty state) URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty
bit 3
bit 2
bit 1
bit 0
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NOTES:
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17.0
Note:
PARALLEL MASTER PORT (PMP)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 13. "Parallel Master Port (PMP)" (DS39713) in the "PIC24F Family Reference Manual" for more information.
Key features of the PMP module include: * Up to 16 Programmable Address Lines * Up to Two Chip Select Lines * Programmable Strobe Options - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe * Address Auto-Increment/Auto-Decrement * Programmable Address/Data Multiplexing * Programmable Polarity on Control Signals * Legacy Parallel Slave Port Support * Enhanced Parallel Slave Support - Address Support - 4-Byte Deep Auto-Incrementing Buffer * Programmable Wait States * Selectable Input Voltage Levels
The Parallel Master Port (PMP) module is a parallel, 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable.
FIGURE 17-1:
PMP MODULE OVERVIEW
Address Bus Data Bus Control Lines
PMA<0> PMALL PMA<1> PMALH
PIC24F Parallel Master Port
Up to 16-Bit Address
PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2 PMBE PMRD PMRD/PMWR PMWR PMENB PMD<7:0> PMA<7:0> PMA<15:8>
EEPROM
Microcontroller
LCD
FIFO Buffer
8-Bit Data
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REGISTER 17-1:
R/W-0 PMPEN bit 15 R/W-0 CSF1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CSF0 R/W-0(1) ALP R/W-0(1) CS2P R/W-0(1) CS1P R/W-0 BEP R/W-0 WRSP U-0 --
PMCON: PARALLEL PORT CONTROL REGISTER
R/W-0 PSIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 R/W-0 PTBEEN R/W-0 PTWREN R/W-0 PTRDEN bit 8 R/W-0 RDSP bit 0
PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Unimplemented: Read as `0' PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8> 00 = Address and data appear on separate pins PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 and PMCS2 function as chip select 01 = PMCS2 functions as chip select, PMCS1 functions as address bit 14 00 = PMCS1 and PMCS2 function as address bits 15 and 14 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) CS2P: Chip Select 2 Polarity bit(1) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS) 0 = Active-low (PMCS1/PMCS) These bits have no effect when their corresponding pins are used as address lines.
bit 14 bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3
Note 1:
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REGISTER 17-1:
bit 2
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) These bits have no effect when their corresponding pins are used as address lines.
bit 1
bit 0
Note 1:
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REGISTER 17-2:
R-0 BUSY bit 15 R/W-0 WAITB1(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 WAITB0(1) R/W-0 WAITM3 R/W-0 WAITM2 R/W-0 WAITM1 R/W-0 WAITM0 R/W-0 WAITE1(1)
PMMODE: PARALLEL PORT MODE REGISTER
R/W-0 IRQM0 R/W-0 INCM1 R/W-0 INCM0 R/W-0 MODE16 R/W-0 MODE1 R/W-0 MODE0 bit 8 R/W-0 WAITE0(1) bit 0
R/W-0 IRQM1
BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy IRQM1:IRQM0: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated INCM1:INCM0: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR<15,13:0> by 1 every read/write cycle 01 = Increment ADDR<15,13:0> by 1 every read/write cycle 00 = No increment or decrement of address MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer MODE1:MODE0: Parallel Port Mode Select bits 11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA and PMD<7:0>) 10 = Master mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA and PMD<7:0>) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY ... 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY) WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
bit 14-13
bit 12-11
bit 10
bit 9-8
bit 7-6
bit 5-2
bit 1-0
Note 1:
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REGISTER 17-3:
R/W-0 CS2 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS1
PMADDR: PARALLEL PORT ADDRESS REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 ADDR<13:8>
R/W-0
ADDR<7:0>
CS2: Chip Select 2 bit 1 = Chip select 2 is active 0 = Chip select 2 is inactive (pin functions as PMA<15>) CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive (pin functions as PMA<14>) ADDR13:ADDR0: Parallel Port Destination Address bits PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes, and as PMADDR only in Master modes.
bit 14
bit 13-0 Note 1:
REGISTER 17-4:
R/W-0 PTEN15 bit 15 R/W-0 PTEN7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14
PMAEN: PARALLEL PORT ENABLE REGISTER
R/W-0 PTEN13 R/W-0 PTEN12 R/W-0 PTEN11 R/W-0 PTEN10 R/W-0 PTEN9 R/W-0 PTEN8 bit 8
R/W-0 PTEN14
R/W-0 PTEN6
R/W-0 PTEN5
R/W-0 PTEN4
R/W-0 PTEN3
R/W-0 PTEN2
R/W-0 PTEN1
R/W-0 PTEN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PTEN15:PTEN14: PMCSx Strobe Enable bits 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O PTEN13:PTEN2: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O
bit 13-2
bit 1-0
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REGISTER 17-5:
R-0 IBF bit 15 R-1 OBE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HS OBUF U-0 -- U-0 -- R-1 OB3E R-1 OB2E R-1 OB1E R-1 OB0E bit 0
PMSTAT: PARALLEL PORT STATUS REGISTER
U-0 -- U-0 -- R-0 IB3F R-0 IB2F R-0 IB1F R-0 IB0F bit 8
R/W-0, HS IBOV
IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as `0' IB3F:IB0F: Input Buffer n Status Full bit 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as `0' OB3E:OB0E: Output Buffer n Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted
bit 14
bit 13-12 bit 11-8
bit 7
bit 6
bit 5-4 bit 3-0
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REGISTER 17-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 RTSECSEL(1) U-0 --
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PMPTTL(2) bit 0
Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit(2) 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set. Refer to Table 1-2 for affected PMP inputs.
bit 0
Note 1: 2:
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FIGURE 17-2:
Master PMD<7:0> PMCS PMRD PMWR
LEGACY PARALLEL SLAVE PORT EXAMPLE
PIC24F Slave PMD<7:0> PMCS PMRD PMWR Address Bus Data Bus Control Lines
FIGURE 17-3:
Master PMA<1:0> PMD<7:0>
ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE
PMA<1:0> PMD<7:0> Write Address Decode PMDOUT1L (0) PIC24F Slave
Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3)
PMCS PMRD PMWR Address Bus Data Bus Control Lines
PMCS PMRD PMWR
PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H (3)
TABLE 17-1:
00 01 10 11
SLAVE MODE ADDRESS RESOLUTION
Output Register (Buffer) PMDOUT1<7:0> (0) PMDOUT1<15:8> (1) PMDOUT2<7:0> (2) PMDOUT2<15:8> (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3)
PMA<1:0>
FIGURE 17-4:
MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS)
PIC24F
PMA<13:0> PMD<7:0>
PMCS1 PMCS2
Address Bus
PMRD PMWR
Data Bus Control Lines
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FIGURE 17-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS)
PIC24F
PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 PMALL PMRD PMWR
Address Bus Multiplexed Data and Address Bus Control Lines
FIGURE 17-6:
MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS)
PIC24F
PMD<7:0> PMA<13:8> PMCS1 PMCS2 PMALL PMALH PMRD PMWR
Multiplexed Data and Address Bus Control Lines
FIGURE 17-7:
EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
373 A<7:0> D<7:0> A<15:8>
PIC24F PMD<7:0> PMALL
A<15:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines
PMALH PMCS1 PMRD PMWR
373
FIGURE 17-8:
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
373 A<7:0> D<7:0> A<14:8> A<14:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines
PIC24F PMD<7:0> PMALL PMA<14:7> PMCS1 PMRD PMWR
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FIGURE 17-9:
PIC24F PMD<7:0> PMALL PMCS1 PMRD PMWR
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
Parallel Peripheral AD<7:0> ALE CS RD WR Address Bus Data Bus Control Lines
FIGURE 17-10:
PIC24F
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)
Parallel EEPROM A D<7:0> CE OE WR Address Bus Data Bus Control Lines
PMA PMD<7:0> PMCS1 PMRD PMWR
FIGURE 17-11:
PIC24F
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)
Parallel EEPROM A D<7:0> A0 CE OE WR Address Bus Data Bus Control Lines
PMA PMD<7:0> PMBE PMCS1 PMRD PMWR
FIGURE 17-12:
PIC24F
LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
LCD Controller D<7:0> RS
PM<7:0> PMA0 PMRD/PMWR PMCS1
R/W
E
Address Bus Data Bus Control Lines
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18.0
Note:
REAL-TIME CLOCK AND CALENDAR (RTCC)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 29. "Real-Time Clock and Calendar (RTCC)" (DS39696) in the "PIC24F Family Reference Manual" for more information.
* * * * * * * * *
The Real-Time Clock and Calendar hardware module has the following features: * Time: Hours, Minutes and Seconds
24-Hour Format (Military Time) Calendar: Weekday, Date, Month and Year Alarm Configurable Year Range: 2000 to 2099 Leap Year Correction BCD Format for Compact Firmware Optimized for Low-Power Operation User Calibration with Auto-Adjust Calibration Range: 2.64 Seconds Error per Month * Requirements: External 32.768 kHz Clock Crystal * Alarm Pulse or Seconds Clock Output on RTCC pin
FIGURE 18-1:
RTCC BLOCK DIAGRAM
RTCC Clock Domain CPU Clock Domain RCFGCAL RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL ALCFGRPT YEAR MTHDAY WKDYHR MINSEC ALMTHDY Compare Registers with Masks Repeat Counter ALRMVAL ALWDHR ALMINSEC
32.768 kHz Input from SOSC Oscillator
Comparator
RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE
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18.1 RTCC Module Registers
The RTCC module registers are organized into three categories: * RTCC Control Registers * RTCC Value Registers * Alarm Value Registers By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR<1:0>, decrements by one until it reaches `00'. Once it reaches `00', the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed.
TABLE 18-2:
ALRMPTR <1:0> 00 01 10 11
18.1.1
REGISTER MAPPING
ALRMVAL REGISTER MAPPING
Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMWD ALRMMNTH -- ALRMSEC ALRMHR ALRMDAY --
To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 18-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR<1:0>, decrements by one until it reaches `00'. Once it reaches `00', the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed.
TABLE 18-1:
RTCPTR <1:0> 00 01 10 11
RTCVAL REGISTER MAPPING
RTCC Value Register Window RTCVAL<15:8> MINUTES WEEKDAY MONTH -- RTCVAL<7:0> SECONDS HOURS DAY YEAR
Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes will decrement the ALRMPTR<1:0> value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR<1:0> being decremented. Note: This only applies to read operations and not write operations.
18.1.2
WRITE LOCK
The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>) to select the desired Alarm register pair (see Table 18-2).
In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL<13>) must be set (refer to Example 18-1).
EXAMPLE 18-1:
asm asm asm asm asm asm
SETTING THE RTCWREN BIT
volatile("disi #5"); volatile("mov #0x55, w7"); volatile("mov w7, _NVMKEY"); volatile("mov #0xAA, w8"); volatile("mov w8, _NVMKEY"); volatile("bset _RCFGCAL, #13");
//set the RTCWREN bit
Note:
To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that the code in Example 18-1 be followed.
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18.1.3 RTCC CONTROL REGISTERS RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
R/W-0 RTCWREN R-0 RTCSYNC R-0 HALFSEC
(3)
REGISTER 18-1:
R/W-0 RTCEN bit 15 R/W-0 CAL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15
(2)
U-0 --
R/W-0 RTCOE
R/W-0 RTCPTR1
R/W-0 RTCPTR0 bit 8
R/W-0 CAL6
R/W-0 CAL5
R/W-0 CAL4
R/W-0 CAL3
R/W-0 CAL2
R/W-0 CAL1
R/W-0 CAL0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as `0' RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled RTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches `00'. RTCVAL<15:8>: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL<7:0>: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR The RCFGCAL Reset value is dependent on type of Reset. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register.
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9-8
Note 1: 2: 3:
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REGISTER 18-1:
bit 7-0
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
CAL7:CAL0: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute ... 10000000 =Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute The RCFGCAL Reset value is dependent on type of Reset. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register.
Note 1: 2: 3:
REGISTER 18-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 U-0 -- U-0 --
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 RTSECSEL(1) R/W-0 PMPTTL(2) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit(2) 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set. Refer to Table 1-2 for affected PMP inputs.
bit 0
Note 1: 2:
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REGISTER 18-3:
R/W-0 ALRMEN bit 15 R/W-0 ARPT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1
ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0
R/W-0 CHIME
ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00 and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h AMASK3:AMASK0: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved - do not use 11xx = Reserved - do not use ALRMPTR1:ALRMPTR0: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches `00'. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented ARPT7:ARPT0: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1.
bit 14
bit 13-10
bit 9-8
bit 7-0
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18.1.4 RTCVAL REGISTER MAPPINGS YEAR: YEAR VALUE REGISTER(1)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-x YRTEN2 R/W-x YRTEN1 R/W-x YRTEN0 R/W-x YRONE3 R/W-x YRONE2 R/W-x YRONE1 R/W-x YRONE0 bit 0
REGISTER 18-4:
U-0 -- bit 15 R/W-x YRTEN3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 bit 3-0 Note 1: U-0 --
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' YRTEN3:YRTEN0: Binary Coded Decimal Value of Year's Tens Digit; Contains a value from 0 to 9 YRONE3:YRONE0: Binary Coded Decimal Value of Year's Ones Digit; Contains a value from 0 to 9 A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 18-5:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 Note 1: U-0 -- U-0 --
MTHDY: MONTH AND DAY VALUE REGISTER(1)
U-0 -- R-x MTHTEN0 R-x MTHONE3 R-x MTHONE2 R-x MTHONE1 R-x MTHONE0 bit 8 R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit; Contains a value of 0 or 1 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day's Tens Digit; Contains a value from 0 to 3 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
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REGISTER 18-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 U-0 --
WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 -- U-0 -- U-0 -- R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 R/W-x HRONE0 bit 0
Unimplemented: Read as `0' WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6 Unimplemented: Read as `0' HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour's Tens Digit; Contains a value from 0 to 2 HRONE3:HRONE0: Binary Coded Decimal Value of Hour's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
REGISTER 18-7:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0
MINSEC: MINUTES AND SECONDS VALUE REGISTER
R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 8
R/W-x MINTEN2
R/W-x SECTEN2
R/W-x SECTEN1
R/W-x SECTEN0
R/W-x SECONE3
R/W-x SECONE2
R/W-x SECONE1
R/W-x SECONE0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute's Tens Digit; Contains a value from 0 to 5 MINONE3:MINONE0: Binary Coded Decimal Value of Minute's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' SECTEN2:SECTEN0: Binary Coded Decimal Value of Second's Tens Digit; Contains a value from 0 to 5 SECONE3:SECONE0: Binary Coded Decimal Value of Second's Ones Digit; Contains a value from 0 to 9
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18.1.5 ALRMVAL REGISTER MAPPINGS ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)
U-0 -- R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 8 U-0 -- R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0
REGISTER 18-8:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 Note 1: U-0 --
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit; Contains a value of 0 or 1 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day's Tens Digit; Contains a value from 0 to 3 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
REGISTER 18-9:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 Note 1: U-0 -- U-0 --
ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 -- U-0 -- U-0 -- R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 R/W-x HRONE0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6 Unimplemented: Read as `0' HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour's Tens Digit; Contains a value from 0 to 2 HRONE3:HRONE0: Binary Coded Decimal Value of Hour's Ones Digit; Contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1.
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REGISTER 18-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 8 R/W-x SECONE0 bit 0
Unimplemented: Read as `0' MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute's Tens Digit; Contains a value from 0 to 5 MINONE3:MINONE0: Binary Coded Decimal Value of Minute's Ones Digit; Contains a value from 0 to 9 Unimplemented: Read as `0' SECTEN2:SECTEN0: Binary Coded Decimal Value of Second's Tens Digit; Contains a value from 0 to 5 SECONE3:SECONE0: Binary Coded Decimal Value of Second's Ones Digit; Contains a value from 0 to 9
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18.2 Calibration 18.3 Alarm
The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will be either added or subtracted from the RTCC timer, once every minute. Refer to the steps below for RTCC calibration: 1. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute. * Configurable from half second to one year * Enabled using the ALRMEN bit (ALCFGRPT<15>, Register 18-3) * One-time alarm and repeat alarm options available
18.3.1
CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVALH:ALRMVALL should only take place when ALRMEN = 0. As shown in Figure 18-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT<13:10>). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs once the alarm is enabled is stored in the lower half of the ALCFGRPT register. When ALCFGRPT = 00 and the CHIME bit = 0 (ALCFGRPT<14>), the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading the lower half of the ALCFGRPT register with FFh. After each alarm is issued, the ALCFGRPT register is decremented by one. Once the register has reached `00', the alarm will be issued one last time, after which, the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the ALCFGRPT register reaches `00', it will roll over to FF and continue counting indefinitely when CHIME = 1.
2.
EQUATION 18-1:
(Ideal Frequency - Measured Frequency) * 60 = Clocks per Minute Ideal Frequency = 32,768 Hz
3.
a) If the oscillator is faster then ideal (negative result form step 2), the RCFGCAL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter once every minute. b) If the oscillator is slower then ideal (positive result from step 2), the RCFGCAL register value needs to be positive. This causes the specified number of clock pulses to be subtracted from the timer counter once every minute.
4.
Divide the number of error clocks per minute by 4 to get the correct CAL value and load the RCFGCAL register with the correct value. (Each 1-bit increment in CAL adds or subtracts 4 pulses). Load the RCFGCAL register with the correct value. Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse. Note: It is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging.
18.3.2
ALARM INTERRUPT
At every alarm event an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Note: Changing any of the registers, other then the RCFGCAL and ALCFGRPT registers and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0.
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FIGURE 18-2: ALARM MASK SETTINGS
Day of the Week Alarm Mask Setting (AMASK3:AMASK0) 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds 0011 - Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month 1001 - Every year(1) Note 1: m m m s s s s s s s
Month
Day
Hours
Minutes
Seconds
h d d m m d d d h h h
h h h h
m m m m
m m m m
s s s s
s s s s
Annually, except when configured for February 29.
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NOTES:
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19.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 30. "Programmable Cyclic Redundancy Check (CRC)" (DS39714) in the "PIC24F Family Reference Manual" for more information.
19.2
Overview
Note:
The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR (X<15:1>) bits and the CRCCON (PLEN3:PLEN0) bits, respectively. Consider the following equation:
EQUATION 19-1:
x
16
CRC POLYNOMIAL
+ x12 + x5 + 1
The programmable CRC generator offers the following features: * User-programmable polynomial CRC equation * Interrupt output * Data FIFO
To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 19-1.
TABLE 19-1:
Bit Name PLEN3:PLEN0 X<15:1>
EXAMPLE CRC SETUP
Bit Value 1111 000100000010000
19.1
Registers
There are four registers used to control programmable CRC operation: * * * * CRCCON CRCXOR CRCDAT CRCWDAT
Note that for the value of X<15:1>, the 12th bit and the 5th bit are set to `1', as required by the equation. The 0 bit required by the equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X<15:1> bits do not have the 0 bit or the 16th bit. The topology of a standard CRC generator is shown in Figure 19-2.
FIGURE 19-1:
CRC SHIFTER DETAILS
PLEN<3:0>
0
1 CRC Shift Register
2
15
Hold XOR DOUT
X1 0 1
Hold
X2 0 1
Hold
X3 0 1
X15 0 1
Hold
OUT IN BIT 0
OUT IN BIT 1
OUT IN BIT 2
OUT IN BIT 15
p_clk
p_clk
p_clk
p_clk
CRC Read Bus
CRC Write Bus
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FIGURE 19-2:
XOR D SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 Q D Q D Q D Q D Q
CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1
p_clk
p_clk
p_clk
p_clk
p_clk
CRC Read Bus
CRC Write Bus
19.3
19.3.1
User Interface
DATA INTERFACE
To start serial shifting, a `1' must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (PLEN<3:0>) > 7, and 16 deep otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. The data must be written as follows: data[5:0] = crc_input[5:0] data[7:6] = `bxx Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of VWORD (VWORD<4:0>) increments by one. The serial shifter starts shifting data into the CRC engine when CRCGO = 1 and VWORD > 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set.
To continually feed data into the CRC engine, the recommended mode of operation is to initially "prime" the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to `1'. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. To empty words already written into a FIFO, the CRCGO bit must be set to `1' and the CRC shifter allowed to run until the CRCMPT bit is set. Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (see Section 19.3.2 "Interrupt Operation"). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done.
19.3.2
INTERRUPT OPERATION
When VWORD4:VWORD0 make a transition from a value of `1' to `0', an interrupt will be generated.
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REGISTER 19-1:
U-0 -- bit 15 R-0 CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-1 CRCMPT U-0 -- R/W-0 CRCGO R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 U-0 --
CRCCON: CRC CONTROL REGISTER
R/W-0 CSIDL R-0 VWORD4 R-0 VWORD3 R-0 VWORD2 R-0 VWORD1 R-0 VWORD0 bit 8 R/W-0 PLEN0 bit 0
Unimplemented: Read as `0' CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD4:VWORD0: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7, or 16 when PLEN3:PLEN0 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty Unimplemented: Read as `0' CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1.
bit 12-8
bit 7
bit 6
bit 5 bit 4
bit 3-0
19.4
19.4.1
Operation in Power Save Modes
SLEEP MODE
19.4.2
IDLE MODE
To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available.
If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes.
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20.0
Note:
10-BIT HIGH-SPEED A/D CONVERTER
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 17. "10-Bit A/D Converter" (DS39705) in the "PIC24F Family Reference Manual" for more information.
A block diagram of the A/D Converter is shown in Figure 20-1. To perform an A/D conversion: 1. Configure the A/D module: a) Select port pins as analog inputs (AD1PCFG<15:0>). b) Select voltage reference source to match expected range on analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:0> and AD1CON3<12:8>). e) Select how conversion results are presented in the buffer (AD1CON1<9:8>). f) Select interrupt rate (AD1CON2<5:2>). g) Turn on A/D module (AD1CON1<15>). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority.
The 10-bit A/D Converter has the following key features: * * * * * * * * * * Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps Up to 16 analog input pins External voltage reference input pins Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes
2.
Depending on the particular device pinout, the 10-bit A/D Converter can have up to 16 analog input pins, designated AN0 through AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details.
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Figure 20-1:
10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus
AVDD AVSS VREF+ VREFAN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 MUX B AN10 AN11 AN12 AN13 AN14 AN15
Sample Control Input MUX Control Pin Config. Control
VR Select
VR+
16
VRVINH VINL VINH
S/H VRVR+
Comparator DAC
10-Bit SAR
Conversion Logic
MUX A
Data Formatting
VINL ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL VINL
VINH
Control Logic
Conversion Control
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REGISTER 20-1:
R/W-0 ADON bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 -- U-0 -- R/W-0 ASAM R/W-0, HCS SAMP U-0 --
AD1CON1: A/D CONTROL REGISTER 1
R/W-0 ADSIDL U-0 -- U-0 -- U-0 -- R/W-0 FORM1 R/W-0 FORM0 bit 8 R/C-0, HCS DONE bit 0
ADON: A/D Operating Mode bit 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as `0' ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' FORM1:FORM0: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC2:SSRC0: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 10x = Reserved 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as `0' ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done
bit 14 bit 13
bit 12-10 bit 9-8
bit 7-5
bit 4-3 bit 2
bit 1
bit 0
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REGISTER 20-2:
R/W-0 VCFG2 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM
AD1CON2: A/D CONTROL REGISTER 2
R/W-0 VCFG0 U-0 r U-0 -- R/W-0 CSCNA U-0 -- U-0 -- bit 8 R/W-0 ALTS bit 0
R/W-0 VCFG1
VCFG2:VCFG0: Voltage Reference Configuration bits: VCFG2:VCFG0 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD VRAVSS AVSS External VREF- pin External VREF- pin AVSS
bit 12 bit 11 bit 10
Reserved Unimplemented: Read as `0' CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer 00-07, user should access data in 08-0F Unimplemented: Read as `0' SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFx<15:8> and ADC1BUFx<7:0>) 0 = Buffer configured as one 16-word buffer (ADC1BUFx<15:0>) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always use MUX A input multiplexer settings
bit 9-8 bit 7
bit 6 bit 5-2
bit 1
bit 0
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REGISTER 20-3:
R/W-0 ADRC bit 15 R/W-0 ADCS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ADCS6 R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1 U-0 --
AD1CON3: A/D CONTROL REGISTER 3
U-0 -- R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0
ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Unimplemented: Read as `0' SAMC4:SAMC0: Auto-Sample Time bits 11111 = 31 TAD ***** 00001 = 1 TAD 00000 = 0 TAD (not recommended) ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 * TCY ****** 00000001 = 2 * TCY 00000000 = TCY
bit 14-13 bit 12-8
bit 7-0
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REGISTER 20-4:
R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 U-0 --
AD1CHS: A/D INPUT SELECT REGISTER
U-0 -- U-0 -- R/W-0 CH0SB3 R/W-0 CH0SB2 R/W-0 CH0SB1 R/W-0 CH0SB0 bit 8 R/W-0 CH0SA0 bit 0
CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SB3:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 ***** 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SA3:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 ***** 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0
bit 14-12 bit 11-8
bit 7
bit 6-4 bit 3-0
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REGISTER 20-5:
R/W-0 PCFG15 bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1
AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 PCFG0 bit 0
R/W-0 PCFG14
PCFG15:PCFG0: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage
REGISTER 20-6:
R/W-0 CSSL15 bit 15 R/W-0 CSSL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0
AD1CSSL: A/D INPUT SCAN SELECT REGISTER
R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8 bit 8
R/W-0 CSSL14
R/W-0 CSSL6
R/W-0 CSSL5
R/W-0 CSSL4
R/W-0 CSSL3
R/W-0 CSSL2
R/W-0 CSSL1
R/W-0 CSSL0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CSSL15:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan
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EQUATION 20-1: A/D CONVERSION CLOCK PERIOD(1)
TAD = TCY(ADCS + 1) TAD -1 ADCS = TCY Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.
FIGURE 20-2:
10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD ANx VT = 0.6V RIC 250 Sampling Switch RSS CHOLD = DAC capacitance = 4.4 pF (Typical) VSS RSS 5 k (Typical)
Rs VA
CPIN 6-11 pF (Typical)
VT = 0.6V
ILEAKAGE 500 nA
Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k.
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FIGURE 20-3:
Output Code (Binary (Decimal))
A/D TRANSFER FUNCTION
11 1111 1111 (1023) 11 1111 1110 (1022)
10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509)
00 0000 0001 (1) 00 0000 0000 (0) 1023*(VR+ - VR-) 512*(VR+ - VR-) (VINH - VINL) VR+ - VRVR+ 1024 0 VR-
1024
Voltage Level
VR- +
VR- +
1024
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VR- +
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21.0
Note:
COMPARATOR MODULE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 19. "Comparator Module" (DS39710) in the "PIC24F Family Reference Manual" for more information.
The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with I/O pins, as well as the on-chip voltage reference. Block diagrams of the various comparator configurations are shown in Figure 21-1.
FIGURE 21-1:
COMPARATOR I/O OPERATING MODES
C1NEG CMCON<6> C1INV C1OUT C1POS
C1EN
C1IN+ C1IN-
VINC1
VIN+ C1OUTEN
C1IN+ CVREF
C2NEG C2IN+ C2INC2POS C2IN+ CVREF VIN+
C2EN
CMCON<7> C2INV C2OUT
VINC2
C2OUTEN
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REGISTER 21-1:
R/W-0 CMIDL bit 15 R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 C2NEG R/W-0 C2POS R/W-0 C1NEG U-0 --
CMCON: COMPARATOR CONTROL REGISTER
R/C-0 C2EVT R/C-0 C1EVT R/W-0 C2EN R/W-0 C1EN R/W-0 C2OUTEN R/W-0 C1OUTEN bit 8 R/W-0 C1POS bit 0
CMIDL: Stop in Idle Mode bit 1 = When device enters Idle mode, module does not generate interrupts. Module is still enabled. 0 = Continue normal module operation in Idle mode Unimplemented: Read as `0' C2EVT: Comparator 2 Event bit 1 = Comparator output changed states 0 = Comparator output did not change states C1EVT: Comparator 1 Event bit 1 = Comparator output changed states 0 = Comparator output did not change states C2EN: Comparator 2 Enable bit 1 = Comparator is enabled 0 = Comparator is disabled C1EN: Comparator 1 Enable bit 1 = Comparator is enabled 0 = Comparator is disabled C2OUTEN: Comparator 2 Output Enable bit 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad C1OUTEN: Comparator 1 Output Enable bit 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 0 = C2 VIN+ > C2 VIN1 = C2 VIN+ < C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VIN-
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
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REGISTER 21-1:
bit 5
CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted C2NEG: Comparator 2 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the Comparator modes. C2POS: Comparator 2 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the Comparator modes. C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the Comparator modes. C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the Comparator modes.
bit 4
bit 3
bit 2
bit 1
bit 0
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22.0
Note:
COMPARATOR VOLTAGE REFERENCE
This data sheet summarizes features of PIC24F group of devices and is not intended to be a comprehensive reference source. Refer to Section 20. "Comparator Voltage Reference Module" (DS39709) in the "PIC24F Family Reference Manual" for more information.
voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output. CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/ 32 step size
22.1
Configuring the Comparator Voltage Reference
The voltage reference module is controlled through the CVRCON register (Register 22-1). The comparator voltage reference provides two ranges of output
FIGURE 22-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ AVDD CVRSS = 1
CVRSS = 0
8R R R R
CVR3:CVR0
CVREN
16 Steps
16-to-1 MUX
R
CVREF
R R R CVRR VREFCVRSS = 1
8R
CVRSS = 0 AVSS
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REGISTER 22-1:
U-0 -- bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 U-0 --
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 CVR0 bit 0
Unimplemented: Read as `0' CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ - VREF0 = Comparator reference source CVRSRC = AVDD - AVSS CVR3:CVR0: Comparator VREF Value Selection 0 CVR3:CVR0 15 bits When CVRR = 1: CVREF = (CVR<3:0>/ 24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (CVR<3:0>/32) * (CVRSRC)
bit 6
bit 5
bit 4
bit 3-0
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23.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 32. "High-Level Device Integration" (DS39719) in the "PIC24F Family Reference Manual" for more information.
TABLE 23-1:
FLASH CONFIGURATION WORDS LOCATIONS
Configuration Word Addresses 1 2 00ABFCh 00FFFCh 0157FCh
Device PIC24FJ64GA PIC24FJ96GA PIC24FJ128GA
00ABFEh 00FFFEh 0157FEh
PIC24FJ128GA010 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation
When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The Configuration bits are reloaded from the Flash Configuration Word on any device Reset. The upper byte of both Flash Configuration Words in program memory should always be `1111 1111'. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation.
23.1
Configuration Bits
The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location F80000h. A complete list is shown in Table 23-1. A detailed explanation of the various bit functions is provided in Register 23-1 through Register 23-4. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes.
23.1.1
CONSIDERATIONS FOR CONFIGURING PIC24FJ128GA010 FAMILY DEVICES
In PIC24FJ128GA010 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the two words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 23-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among five locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device resets.
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REGISTER 23-1:
U-1 -- bit 23 r-x r bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 bit 14 PO = Program-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/PO-1 WINDIS U-1 -- R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN
(1)
FLASH CONFIGURATION WORD 1
U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 16 R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG r-1 r U-1 -- R/PO-1 ICS bit 8 R/PO-1 WDTPS0 bit 0
U-1 --
Unimplemented: Read as `1' Reserved: Program as `0'. Read value unknown. JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Reserved: Program as `1' Unimplemented: Read as `1' ICS: Emulator Pin Placement Select bit 1 = Emulator/debugger uses EMUC2/EMUD2 0 = Emulator/debugger uses EMUC1/EMUD1 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled 0 = Windowed Watchdog Timer enabled; FWDTEN must be `1' Unimplemented: Read as `1' FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial ProgrammingTM (ICSPTM).
bit 13
bit 12
bit 11
bit 10 bit 9 bit 8
bit 7
bit 6
bit 5 bit 4
Note 1:
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REGISTER 23-1:
bit 3-0
FLASH CONFIGURATION WORD 1 (CONTINUED)
WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial ProgrammingTM (ICSPTM).
Note 1:
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REGISTER 23-2:
U-1 -- bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 PO = Program-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/PO-1 FCKSM0 R/PO-1 OSCIOFCN U-1 -- U-1 -- U-1 -- R/PO-1 POSCMD1 U-1 -- U-1 -- U-1 -- U-1 -- R/PO-1 FNOSC2 R/PO-1 FNOSC1 U-1 --
FLASH CONFIGURATION WORD 2
U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0
Unimplemented: Read as `1' IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) enabled 0 = IESO mode (Two-Speed Start-up) disabled Unimplemented: Read as `1' FNOSC2:FNOSC0: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSC2 Pin Configuration bit If POSCMD1:POSCMD0 = 11 or 00: 1 = OSC2/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSC2/CLKO/RC15 functions as port I/O (RC15) If POSCMD1:POSCMD0 = 10 or 01: OSCIOFCN has no effect on OSC2/CLKO/RC15. Unimplemented: Read as `1' POSCMD1:POSCMD0: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected
bit 14-11 bit 10-8
bit 7-6
bit 5
bit 4-2 bit 1-0
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REGISTER 23-3:
U -- bit 23 U -- bit 15 R FAMID1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-14 bit 13-6 bit 5-0 PO = Program-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R FAMID0 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 U -- R FAMID7 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 bit 8 U --
DEVID: DEVICE ID REGISTER
U -- U -- U -- U -- U -- U -- bit 16
Unimplemented: Read as `0' FAMID7:FAMID0: Device Family Identifier bits 00010000 = PIC24FJ128GA010 family DEV5:DEV0: Individual Device Identifier bits 000101 = PIC24FJ64GA006 000110 = PIC24FJ96GA006 000111 = PIC24FJ128GA006 001000 = PIC24FJ64GA008 001001 = PIC24FJ96GA008 001010 = PIC24FJ128GA008 001011 = PIC24FJ64GA010 001100 = PIC24FJ96GA010 001101 = PIC24FJ128GA010
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REGISTER 23-4:
U -- bit 23 R r bit 15 R MAJRV1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15-12 bit 11-9 bit 8-6 bit 5-3 bit 2-0 PO = Program-Once bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R MAJRV0 U -- U -- U -- R DOT2 R DOT1 R DOT0 bit 0 R r R r R r U -- U -- U -- R MAJRV2 bit 8 U --
DEVREV: DEVICE REVISION REGISTER
U -- U -- U -- U -- U -- U -- bit 16
Unimplemented: Read as `0' Reserved: For factory use only Unimplemented: Read as `0' MAJRV2:MAJRV0: Major Revision Identifier bits Unimplemented: Read as `0' DOT2:DOT0: Minor Revision Identifier bits
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23.2 On-Chip Voltage Regulator
FIGURE 23-1:
All of the PIC24FJ128GA010 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ128GA010 incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low ESR capacitor (such as tantalum) must be connected to the VDDCORE/VCAP pin (Figure 23-1). This helps to maintain the stability of the regulator. The recommended value for the filer capacitor, CEFC, is provided in Section 26.1 "DC Characteristics". If ENVREG is tied to VSS, the regulator is disabled. In this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 23-1 for possible configurations.
CONNECTIONS FOR THE ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD): 3.3V PIC24FJ128GA010 VDD ENVREG VDDCORE/VCAP CEFC (10 F typ) VSS
Regulator Disabled (ENVREG tied to ground): 2.5V(1) 3.3V(1) PIC24FJ128GA010 VDD ENVREG VDDCORE/VCAP VSS
23.2.1
ON-CHIP REGULATOR AND POR
Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ128GA010 VDD ENVREG VDDCORE/VCAP VSS
When the voltage regulator is enabled, it takes approximately 20 s for it to generate output. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up.
23.2.2
ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC24FJ128GA010 devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<0>). The brown-out voltage specifications can be found in the PIC24F Family Reference Manual Reset chapter (DS39712).
Note 1:
These are typical operating voltages. Refer to Section 26.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE.
23.2.3
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts.
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23.3
Note:
Watchdog Timer (WDT)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 9. "Watchdog Timer (WDT)" (DS39697) in the "PIC24F Family Reference Manual" for more information.
* When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.
For PIC24FJ128GA010 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS3:WDTPS0 Configuration bits (Flash Configuration Word 1<3:0>), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits), or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered)
23.3.1
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN device Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings.
FIGURE 23-2:
SWDTEN FWDTEN
WDT BLOCK DIAGRAM
LPRC Control FWPSA Prescaler (5-bit/7-bit) 32 kHz 1 ms/4 ms WDT Counter WDTPS3:WDTPS0 Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep
LPRC Input
All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode
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23.4
Note:
JTAG Interface
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 33. "Programming and Diagnostics" (DS39716) in the "PIC24F Family Reference Manual" for more information.
23.6
Note:
In-Circuit Serial Programming
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 33. "Programming and Diagnostics" (DS39716) in the "PIC24F Family Reference Manual" for more information.
PIC24FJ128GA010 family devices implement a JTAG interface, which supports boundary scan device testing as well as in-circuit programming. Refer to the Microchip web site (www.microchip.com) for JTAG support files and additional information.
23.5
Note:
Program Verification and Code Protection
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 33. "Programming and Diagnostics" (DS39716) in the "PIC24F Family Reference Manual" for more information.
PIC24FJ128GA010 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGCx) and data (PGDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
23.7
In-Circuit Debugger
For all devices in the PIC24FJ128GA010 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to 0, internal write and erase operations to program memory are blocked.
When MPLAB(R) ICD 2 is selected as a debugger, the In-Circuit Debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pins. To use the In-Circuit Debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGCx, PGDx and the EMUDx/EMUCx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins.
23.5.1
CONFIGURATION REGISTER PROTECTION
The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the shadow registers which contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Configuration Word Mismatch Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence.
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NOTES:
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24.0 INSTRUCTION SET SUMMARY
The PIC24F instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Word or byte-oriented operations Bit-oriented operations Literal operations Control operations The literal instructions that involve data movement may use some of the following operands: * A literal value to be loaded into a W register or file register (specified by the value of `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand which is a register `Wb' without any address modifier * The second source operand which is a literal value * The destination of the result (only if not the same as the first source operand) which is typically a register `Wd' with or without an address modifier The control instructions may use some of the following operands: * A program memory address * The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made doubleword instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles.
Table 24-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 24-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand which is typically a register `Wb' without any address modifier * The second source operand which is typically a register `Ws' with or without an address modifier * The destination of the result which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value `f' * The destination, which could either be the file register `f' or the W0 register, which is denoted as `WREG' Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: * The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb')
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TABLE 24-1:
Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by "text" Means "content of text" Means "the location addressed by text" Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0000h...1FFFh} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16384} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388608}; LSB must be `0' Field does not require an entry, may be blank Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (Direct Addressing) One of 16 working registers {W0..W15} One of 16 destination working registers {W0..W15} One of 16 source working registers {W0..W15} W0 (working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
SYMBOLS USED IN OPCODE DESCRIPTIONS
Description
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TABLE 24-2:
Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BRA BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSW BTG BTSC BSET BSET BSW.C BSW.Z BTG BTG BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4
INSTRUCTION SET OVERVIEW
Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None
1 None (2 or 3) 1 None (2 or 3)
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TABLE 24-2:
Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CLR CALL CALL CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CPB CP0 CP0 CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb - Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb - Ws - C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if Wn = Decimal Adjust Wn f = f -1 WREG = f -1 Wd = Ws - 1 f=f-2 WREG = f - 2 Wd = Ws - 2 Disable Interrupts for k Instruction Cycles Signed 16/16-Bit Integer Divide Signed 32/16-Bit Integer Divide Unsigned 16/16-Bit Integer Divide Unsigned 32/16-Bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected
1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z
1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C
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TABLE 24-2:
Assembly Mnemonic GOTO INC GOTO GOTO INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP POP NOP NOPR POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-Bit Literal to Wn Move 8-Bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None
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TABLE 24-2:
Assembly Mnemonic PWRSAV RCALL REPEAT RESET RETFIE RETLW RETURN RLC PWRSAV RCALL RCALL REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP TBLRDH SWAP.b SWAP TBLRDH f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd #lit10,Wn
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f - WREG WREG = f - WREG Wn = Wn - lit10 Wd = Wb - Ws Wd = Wb - lit5 f = f - WREG - (C) WREG = f - WREG - (C) Wn = Wn - lit10 - (C) Wd = Wb - Ws - (C) Wd = Wb - lit5 - (C) f = WREG - f WREG = WREG - f Wd = Ws - Wb Wd = lit5 - Wb f = WREG - f - (C) WREG = WREG - f - (C) Wd = Ws - Wb - (C) Wd = lit5 - Wb - (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog<23:16> to Wd<7:0> # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None
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TABLE 24-2:
Assembly Mnemonic TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Description Read Prog<15:0> to Wd Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N
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NOTES:
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25.0 DEVELOPMENT SUPPORT
25.1
The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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25.2 MPLAB C Compilers for Various Device Families 25.5 MPLINK Object Linker/ MPLIB Object Librarian
The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
25.3
HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.
25.6
MPLAB Assembler, Linker and Librarian for Various Device Families
25.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
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25.7 MPLAB SIM Software Simulator 25.9
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.
25.8
MPLAB REAL ICE In-Circuit Emulator System
25.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
25.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.
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26.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ128GA010 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ128GA010 are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +2.8V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2).
FIGURE 26-1:
FREQUENCY/VOLTAGE GRAPH
3.00V 2.75V 2.50V Voltage VDDCORE(1) 2.25V 2.00V 2.75V
16 MHz Frequency
Note 1:
32 MHz
When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE VDD 3.6V.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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26.1 DC Characteristics
OPERATING MIPS vs. VOLTAGE
Temp Range (in C) -40C to +85C Max MIPS PIC24FJ128GA010 Family 16
TABLE 26-1:
VDD Range (in Volts) 2.0-3.6V
TABLE 26-2:
THERMAL OPERATING CONDITIONS
Rating Symbol TJ TA Min -40 -40 Typ -- -- Max +125 +85 Unit C C
PIC24FJ128GA010 Family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - IOH) I/O Pin Power Dissipation: PI/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/JA W
PD
PINT + PI/O
W
TABLE 26-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ 50 69.4 76.6 Max -- -- -- Unit C/W C/W C/W Notes (Note 1) (Note 1) (Note 1)
Package Thermal Resistance, 14x14x1 mm TQFP Package Thermal Resistance, 12x12x1 mm TQFP Package Thermal Resistance, 10x10x1 mm TQFP Note 1:
JA JA JA
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 26-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions
DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VDD VDDCORE DC12 DC16 VDR VPOR RAM Data Retention Voltage(2) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Characteristic
2.7 VDDCORE 2.0 1.5 --
-- -- -- -- VSS
3.6 3.6 2.75 -- --
V V V V V
Regulator enabled Regulator disabled Regulator disabled
DC17
SVDD
0.05
--
--
V/ms
0-3.3V in 0.1s 0-2.5V in 60 ms
Note 1: 2:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data.
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TABLE 26-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC20 DC20a DC20b DC20d DC20e DC20f DC23 DC23a DC23b DC23d DC23e DC23f DC24 DC24a DC24b DC24d DC24e DC24f DC31 DC31a DC31b DC31d DC31e DC31f Note 1: 2: Typical(1)
Operating Current (IDD)(2) 1.6 1.6 1.6 1.6 1.6 1.6 6.0 6.0 6.0 6.0 6.0 6.0 20 20 20 20 20 20 70 100 200 70 100 200 4.0 4.0 4.0 4.0 4.0 4.0 12 12 12 12 12 12 32 32 32 32 32 32 150 200 400 150 200 400 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.6V(4) 2.5V(3) LPRC (31 kHz) 3.6V(4) 2.5V(3) 16 MIPS 3.6V(4) 2.5V(3) 4 MIPS 3.6V(4) 2.5V(3) 1 MIPS
3: 4:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and PMD bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD).
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TABLE 26-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC40 DC40a DC40b DC40d DC40e DC40f DC43 DC43a DC43b DC43d DC43e DC43f DC47 DC47a DC47b DC47c DC47d DC47e DC51 DC51a DC51b DC51d DC51e DC51f Note 1: 2: 3: 4: Typical(1)
Idle Current (IIDLE): Core Off, Clock On Base Current(2) 0.7 0.7 0.7 0.7 0.7 0.7 2.1 2.1 2.1 2.1 2.1 2.1 6.8 6.8 6.8 6.8 6.8 6.8 150 150 150 150 150 150 2 2 2 2 2 2 4 4 4 4 4 4 8 8 8 8 8 8 500 500 500 500 500 500 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.6V(4) 2.5V(3) LPRC (31 kHz) 3.6V(4) 2.5V(3) 16 MIPS 3.6V(4) 2.5V(3) 4 MIPS 3.6V(4) 2.5V(3) 1 MIPS
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with core off, clock on, PMD bits set and all modules turned off. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD).
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TABLE 26-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60 DC60a DC60b DC60f DC60g DC60h DC61 DC61a DC61b DC61f DC61g DC61h DC62 DC62a DC62b DC62f DC62g DC62h Note 1: 2: 3: 4: 5: Typical(1)
Power-Down Current (IPD)(2) 3 3 100 20 27 120 10 10 10 10 10 10 8 8 8 8 8 8 25 45 600 40 60 600 25 25 25 25 25 25 15 15 15 15 15 15 A A A A A A A A A A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.6V(4) 2.0V(3) RTCC + Timer1 w/32 kHz Crystal: IRTCC(5) 3.6V(4) 2.0V(3) Watchdog Timer Current: IWDT(5) 3.6V(4) 2.0V(3) Base Power-Down Current(5)
Module Differential Current
Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. Unused PMD bits are set. VREGS bit is clear. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
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TABLE 26-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O pins with ST buffer: I/O pins with TTL buffer: MCLR OSC1 (XT mode) OSC1 (HS mode) I/O pins with I2C buffer: I/O pins with SMBus buffer: Input High Voltage(4) I/O pins with ST buffer: With Analog Functions Digital-Only I/O pins with TTL buffer: With Analog Functions Digital-Only MCLR OSC1 (XT mode) OSC1 (HS mode) I/O pins with 12C buffer: With Analog Functions Digital-Only
I/O pins with SMBUS buffer:
VSS VSS VSS VSS VSS VSS VSS
-- -- -- -- -- -- --
0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8
V V V V V V V SMBus enabled
0.8 VDD 0.8 VDD 0.25 VDD+ 0.8 0.25 VDD+ 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 2.1 50 -- -- -- --
-- -- -- -- -- -- -- -- --
VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5 VDD 5.5
V V V V V V V V V V V A A A A A
DI21
DI25 DI26 DI27 DI28
DI29
With Analog Functions Digital-Only ICNPU CNxx Pull-up Current IIL Input Leakage Current(2,3) I/O Ports Analog Input pins MCLR OSC1
2.5V VPIN VDD VDD = 3.3V, VPIN = VSS VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes
DI30 DI50 DI51 DI55 DI56 Note 1: 2:
250 -- -- -- --
400 +1 +1 +1 +1
3: 4:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-2 for I/O pins buffer types.
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TABLE 26-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 Sym VOL Characteristic Output Low Voltage I/O Ports OSC2/CLKO Output High Voltage I/O Ports 3.0 2.4 1.65 1.4 DO26 Note 1: OSC2/CLKO 2.4 1.4 -- -- -- -- -- -- -- -- -- -- -- -- V V V V V V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V IOH = -3.0 mA, VDD = 2.0V IOH = -6.0 mA, VDD = 3.6V IOH = -3.0 mA, VDD = 2.0V -- -- -- -- -- -- -- -- 0.4 0.4 0.4 0.4 V V V V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-10: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS Param No. D130 D131 D132B D133A D134 D135 Note 1: Sym Characteristic Program Flash Memory EP VPR Cell Endurance VDD for Read 100 VMIN 2.25 -- 20 -- 1K -- -- 3 -- 10 -- 3.6 3.6 -- -- -- E/W V V ms Year mA Provided no other specifications are violated -40C to +85C VMIN = Minimum operating voltage Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions
VPEW VDD for Self-Timed Erase/ Write TIW Self-Timed Write Cycle Time
TRETD Characteristic Retention IDDP Supply Current during Programming
Data in "Typ" column is at 3.3V, 25C unless otherwise stated.
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TABLE 26-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40C < TA < +85C (unless otherwise stated) Param Symbol No. CEFC TVREG TPWRT Characteristics Min -- 4.7 -- -- Typ 2.5 10 10 64 Max -- -- -- -- Units V F s ms Series resistance < 3 Ohm recommended; < 5 Ohm required. ENVREG = VDD ENVREG = VSS Comments
VRGOUT Regulator Output Voltage External Filter Capacitor Value
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26.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ128GA010 AC characteristics and timing parameters.
TABLE 26-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in Section 26.1 "DC Characteristics".
FIGURE 26-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 - for OSC2
Load Condition 1 - for all pins except OSC2 VDD/2 RL
Pin VSS
CL
Pin VSS
CL
RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output
TABLE 26-13: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param Symbol No. DO50 COSC2 Characteristic OSC2/CLKO pin Min -- Typ(1) -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSC1. EC mode In I2CTM mode
DO56 DO58 Note 1:
CIO CB
All I/O pins and OSC2 SCLx, SDAx
-- --
-- --
50 400
pF pF
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
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FIGURE 26-3:
Q4
EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSC1
OS20 OS25 OS30 OS30 OS31 OS31
CLKO
OS40 OS41
TABLE 26-14: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min DC 3 3.5 3.5 10 31 -- 62.5 0.45 x TOSC -- -- -- Typ(1) -- -- -- -- -- -- -- -- -- -- 6 6 Max 32 8 10 8 32 33 -- DC -- 20 10 10 Units MHz MHz MHz MHz MHz kHz -- ns ns ns ns ns EC EC EC ECPLL XT XTPLL HS SOSC See parameter OS10 for FOSC value Conditions
FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency
OS20 OS25 OS30 OS31 OS40 OS41
TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2)
TosL, External Clock in (OSC1) TosH High or Low Time TosR, External Clock in (OSC1) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time(3)
Note 1: 2:
3:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
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TABLE 26-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
AC CHARACTERISTICS Param No. OS50 OS51 OS52 OS53 Note 1: 2: Sym FPLLI FSYS Characteristic(1) PLL Input Frequency Range(2) On-Chip VCO System Frequency Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min 3 8 -- -2 Typ(2) -- -- -- 1 Max 8 32 2 +2 Units MHz MHz ms % Conditions ECPLL, HSPLL, XTPLL modes
TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter)
These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-16: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F20 FRC Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions
Internal FRC Accuracy @ 8 MHz(1) -2 -5 -- -- +2 +5 % % +25C -40C TA +85C Vdd = 3.0 - 3.6V Vdd = 3.0 - 3.6V
Legend: TBD = To Be Determined Note 1: Frequency calibrated at 25C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
TABLE 26-17: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F21 Note 1: Characteristic LPRC @ 31 kHz(1) -15 -- +15 % -40C TA +85C VDD = 3.0 - 3.6V Change of LPRC frequency as VDD changes. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions
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FIGURE 26-4: CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 26-2 for load conditions. New Value
TABLE 26-18: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -- -- 20 2 Typ(1) 10 10 -- -- Max 25 25 -- -- Units ns ns ns TCY Conditions
Data in "Typ" column is at 3.3V, 25C unless otherwise stated.
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TABLE 26-19: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C
Param Symbol No.
AD01 AVDD
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply Module VDD Supply Greater of VDD - 0.3 or 2.0 VSS - 0.3 AVSS + 1.7 AVSS AVSS - 0.3 -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD - 1.7 AVDD + 0.3 V
AD02 AD05 AD06 AD07
AVSS VREFH VREFL VREF
Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage
-- -- -- --
V V V V
Reference Inputs
Analog Input AD10 AD11 AD12 VINH-VINL Full-Scale Input Span VIN -- Absolute Input Voltage Leakage Current VREFL AVSS - 0.3 -- 0.001 VREFH AVDD + 0.3 0.610 V V A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V, Source Impedance = 2.5 k VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k See Note 2
AD13
--
Leakage Current
--
0.001
0.610
A
AD14 AD17
VINL RIN
Absolute VINL Input Voltage Recommended Impedance of Analog Voltage Resolution Integral Nonlinearity(2) Differential Nonlinearity(2) Gain Error(2) Offset Error(2) Monotonicity(1)
AVSS - 0.3 -- --
AVDD/2 2.5K
V
ADC Accuracy AD20a Nr AD21a INL AD22a DNL AD23a GERR AD24a EOFF AD25a -- 10 data bits -- -- -- -- -- +1 +0.5 +1 +1 -- <2 <1 3 2 -- bits LSb LSb LSb LSb -- VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Guaranteed
Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference
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TABLE 26-20: ADC CONVERSION TIMING REQUIREMENTS(1)
AC CHARACTERISTICS Param No. AD50 AD51 Sym TAD tRC Characteristic ADC Clock Period ADC Internal RC Oscillator Period Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min 75 -- Typ(1) -- 250 Max -- -- Units ns ns Conditions TCY = 75ns, ADxCON3 in default state
Conversion Rate AD55 AD56 AD57 AD61 tCONV Conversion Time FCNV Throughput Rate tSAMP Sample Time tPSS Sample Start Delay from Setting Sample bit (SAMP) -- -- -- 2 12 -- 1 -- -- 500 -- 3 TAD ksps TAD TAD
Clock Parameters
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
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27.0
27.1
PACKAGING INFORMATION
Package Marking Information
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP (12x12x1 mm)
PIC24FJ128 GA006-I/ PT e3 0710017 Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC24FJ128GA 008-I/PT e3 0710017
100-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC24FJ128GA 010-I/PT e3 0710017
100-Lead TQFP (14x14x1 mm)
Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC24FJ128GA 010-I/PF e3 0710017
Legend: XX...X Y YY WW NNN * Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2009 Microchip Technology Inc.
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27.2 Package Details
The following sections give the technical details of the packages.
64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1
E e E1
N b NOTE 1 123 NOTE 2 A c A2
L
A1
L1
Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.17 11 11 0 - 0.95 0.05 0.45 MIN
MILLIMETERS NOM 64 0.50 BSC - 1.00 - 0.60 1.00 REF 3.5 12.00 BSC 12.00 BSC 10.00 BSC 10.00 BSC - 0.22 12 12 0.20 0.27 13 13 7 1.20 1.05 0.15 0.75 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-085B
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80-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1
E e E1
b
N 12 3 A c
NOTE 1
NOTE 2
L
A1 L1
A2
Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.17 11 11 0 - 0.95 0.05 0.45 MIN
MILLIMETERS NOM 80 0.50 BSC - 1.00 - 0.60 1.00 REF 3.5 14.00 BSC 14.00 BSC 12.00 BSC 12.00 BSC - 0.22 12 12 0.20 0.27 13 13 7 1.20 1.05 0.15 0.75 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-092B
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100-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1
e E E1
b
N 1 23
NOTE 1 c
NOTE 2
A L
Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.13 11 11 0 - 0.95 0.05 0.45 MIN
A1
L1
MILLIMETERS NOM 100 0.40 BSC - 1.00 - 0.60 1.00 REF 3.5 14.00 BSC 14.00 BSC 12.00 BSC 12.00 BSC - 0.18 12 12 0.20 0.23 13 13 7 1.20 1.05 0.15 0.75 MAX
A2
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-100B
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100-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1
e
E1 E
b N NOTE 1 1 23 NOTE 2 A
c
L A1 L1
A2
Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.17 11 11 0 - 0.95 0.05 0.45 MIN
MILLIMETERS NOM 100 0.50 BSC - 1.00 - 0.60 1.00 REF 3.5 16.00 BSC 16.00 BSC 14.00 BSC 14.00 BSC - 0.22 12 12 0.20 0.27 13 13 7 1.20 1.05 0.15 0.75 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-110B
(c) 2009 Microchip Technology Inc.
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NOTES:
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APPENDIX A: REVISION HISTORY
Revision A (September 2005)
Original data sheet for PIC24FJ128GA010 family devices.
Revision B (March 2006)
Update of electrical specifications.
Revision C (June 2006)
Update of electrical specifications.
Revision D (September 2007)
Minor changes in the overall data sheet
Revision E (October 2009)
Updated to remove Preliminary status.
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NOTES:
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INDEX
A
AC Characteristics .......................................................... 219 Internal RC Accuracy ........................................ 221 Load Conditions ........................................................ 219 Temperature and Voltage Specifications .................. 219 Alternate Interrupt Vector Table (AIVT)............................... 59 Arithmetic Logic Unit (ALU)................................................. 26 Assembler MPASM Assembler ................................................... 208
B
Baud Rate Error Calculation (BRGH = 0) ......................... 140 Block Diagrams 10-Bit High-Speed A/D Converter ............................. 174 16-Bit Timer1 Module................................................ 105 8-Bit Multiplexed Address and Data Application ....... 156 Accessing Program Memory with Table Instructions .. 44 Addressable Parallel Slave Port ............................... 154 Comparator I/O Operating Modes............................. 183 Comparator Voltage Reference ................................ 187 Connections for On-Chip Voltage Regulator............. 195 Device Clock ............................................................... 93 I2C ............................................................................. 132 Input Capture ............................................................ 113 LCD Control .............................................................. 156 Legacy Parallel Slave Port ........................................ 154 Master Mode, Demultiplexed Addressing ................. 154 Master Mode, Fully Multiplexed Addressing ............. 155 Master Mode, Partially Multiplexed Addressing ........ 155 Multiplexed Addressing Application .......................... 155 Output Compare Module........................................... 115 Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data) ... 156 Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data) ..... 156 Partially Multiplexed Addressing Application ............ 155 PIC24F CPU Core ...................................................... 22 PIC24FJ128GA010 Family (General) ......................... 12 PMP Module ............................................................. 147 Program Space Visibility Operation ............................ 45 Reset System.............................................................. 53 RTCC ........................................................................ 157 Shared Port Structure ............................................... 103 SPI Master, Frame Master Connection..................... 129 SPI Master, Frame Slave Connection....................... 129 SPI Master/Slave Connection (Enhanced Buffer Modes) 128 SPI Master/Slave Connection (Standard Mode) ....... 128 SPI Slave, Frame Master Connection....................... 129 SPI Slave, Frame Slave Connection......................... 129 SPIx Module (Enhanced Mode) ................................ 123 SPIx Module (Standard Mode).................................. 122 Timer2 and Timer4 (16-Bit Synchronous) ................. 109 Timer2/3 and Timer4/5 (32-Bit) ................................. 108 Timer3 and Timer5 (16-Bit Asynchronous) ............... 109 UART ........................................................................ 139 Watchdog Timer (WDT) ............................................ 196 Brown-out Reset (BOR) and On-Chip Voltage Regulator ................................ 195
MPLAB C18 .............................................................. 208 Clock Switching and Clock Frequency................................................ 101 Enabling...................................................................... 99 Operation .................................................................... 99 Oscillator Sequence.................................................... 99 Code Examples Basic Code Sequence for Clock Switching............... 100 Erasing a Program Memory Block .............................. 50 Initiating a Programming Sequence............................ 51 Loading Write Buffers ................................................. 51 Port Write/Read ........................................................ 104 Programming a Single Word of Flash Program Memory 52 PWRSAV Instruction Syntax..................................... 101 Comparator Module .......................................................... 183 Comparator Voltage Reference ........................................ 187 Configuring ............................................................... 187 Configuration Bits ............................................................. 189 Configuration Register Protection..................................... 197 Configuring Analog Port Pins............................................ 104 Core Features....................................................................... 9 16-Bit Architecture ........................................................ 9 Easy Migration ............................................................ 10 Oscillator Options, Features ......................................... 9 Power-Saving Technology............................................ 9 CPU .................................................................................... 21 Control Registers ........................................................ 24 Programmer's Model .................................................. 23 CPU Clocking Scheme ....................................................... 94 CRC Example Setup ......................................................... 169 Operation in Power Save Modes .............................. 171 Overview................................................................... 169 Registers .................................................................. 169 User Interface ........................................................... 170 Customer Change Notification Service............................. 237 Customer Notification Service .......................................... 237 Customer Support............................................................. 237
D
Data Memory Address Space ........................................................... 29 Width .................................................................. 29 Memory Map for PIC24F128GA010 Family Devices.. 29 Near Data Space ........................................................ 30 Organization and Alignment ....................................... 30 SFR Space ................................................................. 30 Software Stack ........................................................... 42 DC Characteristics............................................................ 212 I/O Pin Input Specifications....................................... 216 I/O Pin Output Specifications.................................... 217 Idle Current (IIDLE) .................................................... 214 Operating Current (IDD) ............................................ 213 Operating MIPS vs. Voltage ..................................... 212 Power-Down Current (IPD)........................................ 215 Program Memory ...................................................... 217 Temperature and Voltage Specifications.................. 212 Thermal Operating Conditions.................................. 212 Thermal Packaging Characteristics .......................... 212 Development Support ....................................................... 207
C
C Compilers
DS39747E-page 233
(c) 2009 Microchip Technology Inc.
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E
Electrical Characteristics................................................... 211 Absolute Maximum Ratings ...................................... 211 ENVREG pin ..................................................................... 195 Equations A/D Conversion Clock Period ................................... 180 Calculating the PWM Period ..................................... 117 Calculation for Maximum PWM Resolution............... 117 Relationship Between Device and SPI Clock Speed ...... .......................................................................... 130 UART Baud Rate with BRGH = 0 ............................. 140 UART Baud Rate with BRGH = 1 ............................. 140 Errata .................................................................................... 8
M
Memory Organization ......................................................... 27 Microchip Internet Web Site.............................................. 237 Mode of Operation ............................................................ 115 MPLAB ASM30 Assembler, Linker, Librarian ................... 208 MPLAB Integrated Development Environment Software.. 207 MPLAB PM3 Device Programmer .................................... 210 MPLAB REAL ICE In-Circuit Emulator System ................ 209 MPLINK Object Linker/MPLIB Object Librarian ................ 208
O
Open-Drain Configuration................................................. 104 Oscillator Configuration ...................................................... 93 Clock Switching Mode Configuration Bits ................... 94 Control Registers ........................................................ 95 CLKDIV............................................................... 95 OSCCON............................................................ 95 OSCTUN ............................................................ 95 Output Compare ............................................................... 115
F
Flash Configuration Words.......................................... 28, 189 Flash Program Memory....................................................... 47 Control Registers ........................................................ 48 Enhanced ICSP .......................................................... 48 Operations .................................................................. 48 Programming Algorithm .............................................. 50 RTSP Operation.......................................................... 48 Table Instructions........................................................ 47 FSCM and Device Resets ...................................................... 57 Delay for Crystal and PLL Clock Sources ................... 57
P
Packaging ......................................................................... 225 Details....................................................................... 226 Marking ..................................................................... 225 Pad Configuratiuon Map ..................................................... 39 Parallel Master Port (PMP) ............................................... 147 POR and Long Oscillator Start-up Times ........................... 57 Power-on Reset (POR) and On-Chip Voltage Regulator................................ 195 Power-Saving Features .................................................... 101 Power-Saving Modes Doze ......................................................................... 102 Instruction-Based...................................................... 101 Idle.................................................................... 102 Sleep ................................................................ 101 Program Address Space..................................................... 27 Memory Map for PIC24FJ128GA010 Family Devices 27 Program and Data Memory Spaces Interfacing ................................................................... 42 Program Memory Data Access Using Table Instructions ........................ 44 Hard Memory Vectors................................................. 28 Interrupt Vector ........................................................... 28 Organization ............................................................... 28 Reading Data Using Program Space Visibility............ 45 Reset Vector ............................................................... 28 Table Instructions TBLRDH ............................................................. 44 TBLRDL.............................................................. 44 Program Space Address Construction ................................................. 43 Addressing.................................................................. 42 Data Access From, Address Generation .................... 43 Program Verification and Code Protection ....................... 197 Programmer's Model .......................................................... 21 Pulse-Width Modulation Mode.......................................... 117 Duty Cycle ................................................................ 117 Period ....................................................................... 117
I
I/O Ports ............................................................................ 103 Parallel I/O (PIO)....................................................... 103 Write/Read Timing .................................................... 104 I2C Clock Rates............................................................... 133 Communicating as Master in a Single Master Environment............................... 131 Setting Baud Rate When Operating as Bus Master.. 133 Slave Address Masking ............................................ 133 Implemented Interrupt Vectors (table)................................. 61 In-Circuit Debugger ........................................................... 197 In-Circuit Serial Programming (ICSP) ............................... 197 Input Capture .................................................................... 113 Registers ................................................................... 114 Input Change Notification.................................................. 104 Instruction Set Overview ................................................................... 201 Summary................................................................... 199 Inter-Integrated Circuit (I2C).............................................. 131 Internal RC Oscillator Use with WDT ........................................................... 196 Internet Address................................................................ 237 Interrupt Control and Status Registers................................ 62 IECx ............................................................................ 62 IFSx............................................................................. 62 INTCON1, INTCON2 .................................................. 62 IPCx ............................................................................ 62 Interrupt Controller .............................................................. 59 Interrupt Setup Procedures ................................................. 91 Initialization ................................................................. 91 Interrupt Disable.......................................................... 91 Interrupt Service Routine (ISR) ................................... 91 Trap Service Routine (TSR)........................................ 91 Interrupt Vector Table (IVT) ................................................ 59 Interrupts Coincident with Power Save Instructions.......... 102
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(c) 2009 Microchip Technology Inc.
R
Reader Response ............................................................. 238 Register Map ADC ............................................................................ 37 CPU Core.................................................................... 31 CRC ............................................................................ 41 Dual Comparator......................................................... 40 I2C1 ............................................................................ 35 I2C2 ............................................................................ 35 ICN .............................................................................. 33 Input Capture .............................................................. 34 Interrupt Controller ...................................................... 32 NVM ............................................................................ 41 Output Compare ......................................................... 34 Parallel Master/Slave Port .......................................... 40 PMD ............................................................................ 41 PORTA........................................................................ 37 PORTB........................................................................ 38 PORTC ....................................................................... 38 PORTD ....................................................................... 38 PORTE........................................................................ 39 PORTF ........................................................................ 39 PORTG ....................................................................... 39 Real-Time Clock and Calendar ................................... 40 SPI1 ............................................................................ 36 SPI2 ............................................................................ 36 System ........................................................................ 41 Timer ........................................................................... 33 UART1 ........................................................................ 36 UART2 ........................................................................ 36 Registers AD1CHS (A/D Input Select) ...................................... 178 AD1CON1 (A/D Control 1) ........................................ 175 AD1CON2 (A/D Control 2) ........................................ 176 AD1CON3 (A/D Control 3) ........................................ 177 AD1CSSL (A/D Input Scan Select) ........................... 179 AD1PCFG (A/D Port Configuration).......................... 179 ALCFGRPT (Alarm Configuration)............................ 161 ALMINSEC (Alarm Minutes and Seconds Value) ..... 165 ALMTHDY (Alarm Month and Day Value) ................ 164 ALWDHR (Alarm Weekday and Hours Value) .......... 164 CLKDIV (Clock Divider) .............................................. 97 CMCON (Comparator Control) ................................. 184 CORCON (Core Control) ...................................... 25, 63 CRCCON (CRC Control) .......................................... 171 CVRCON (Comparator Voltage Reference Control). 188 DEVID (Device ID) .................................................... 193 DEVREV (Device Revision) ...................................... 194 Flash Configuration Word 1 ...................................... 190 Flash Configuration Word 2 ...................................... 192 I2CxCON (I2Cx Control) ........................................... 134 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 138 I2CxSTAT (I2Cx Status) ........................................... 136 ICxCON (Input Capture x Control) ............................ 114 IEC0 (Interrupt Enable Control 0) ............................... 71 IEC1 (Interrupt Enable Control 1) ............................... 72 IEC2 (Interrupt Enable Control 2) ............................... 73 IEC3 (Interrupt Enable Control 3) ............................... 74 IEC4 (Interrupt Enable Control 4) ............................... 75 IFS0 (Interrupt Flag Status 0) ..................................... 66 IFS1 (Interrupt Flag Status 1) ..................................... 67
IFS2 (Interrupt Flag Status 2) ..................................... 68 IFS3 (Interrupt Flag Status 3) ..................................... 69 IFS4 (Interrupt Flag Status 4) ..................................... 70 INTCON1 (Interrupt Control 1).................................... 64 INTCON2 (Interrupt Control 2).................................... 65 IPC0 (Interrupt Priority Control 0) ............................... 76 IPC1 (Interrupt Priority Control 1) ............................... 77 IPC10 (Interrupt Priority Control 10) ........................... 86 IPC11 (Interrupt Priority Control 11) ........................... 86 IPC12 (Interrupt Priority Control 12) ........................... 87 IPC13 (Interrupt Priority Control 13) ........................... 88 IPC15 (Interrupt Priority Control 15) ........................... 89 IPC16 (Interrupt Priority Control 16) ........................... 90 IPC2 (Interrupt Priority Control 2) ............................... 78 IPC3 (Interrupt Priority Control 3) ............................... 79 IPC4 (Interrupt Priority Control 4) ............................... 80 IPC5 (Interrupt Priority Control 5) ............................... 81 IPC6 (Interrupt Priority Control 6) ............................... 82 IPC7 (Interrupt Priority Control 7) ............................... 83 IPC8 (Interrupt Priority Control 8) ............................... 84 IPC9 (Interrupt Priority Control 9) ............................... 85 MINSEC (Minutes and Seconds Value).................... 163 MTHDY (Month and Day Value) ............................... 162 NVMCON (Flash Memory Control) ............................. 49 OCxCON Output Compare x Control) ...................... 119 OSCCON (Oscillator Control) ..................................... 95 OSCTUN (FRC Oscillator Tune)................................. 98 PMADDR (Parallel Port Address) ............................. 151 PMAEN (Parallel Port Enable).................................. 151 PMCON (Parallel Port Control)................................. 148 PMMODE (Parallel Port Mode)................................. 150 PMSTAT (Parallel Port Status) ................................. 152 RCFGCAL (RTCC Calibration and Configuration).... 159 RCON (Reset Control)................................................ 54 SPIxCON1 (SPIx Control 1)...................................... 126 SPIxCON2 (SPIx Control 2)...................................... 127 SPIxSTAT (SPIx Status and Control) ....................... 124 SR (CPU STATUS)............................................... 24, 63 T1CON (Timer1 Control) .......................................... 106 TxCON (Timer2/4 Control)........................................ 110 TyCON (Timer3/5 Control)........................................ 111 UxMODE (UARTx Mode).......................................... 142 UxSTA (UARTx Status and Control)......................... 144 WKDYHR (Weekday and Hours Value).................... 163 YEAR (Year Value)................................................... 162 Reset Sequence ................................................................. 59 Resets................................................................................. 53 Clock Source Selection............................................... 55 Device Times .............................................................. 55 Revision History................................................................ 231 RTCC Alarm ........................................................................ 166 Configuring ....................................................... 166 Interrupt ............................................................ 166 ALRMVAL Register Mappings .................................. 164 Calibration ................................................................ 166 Control Registers ...................................................... 159 Module Registers...................................................... 158 Mapping............................................................ 158 RTCVAL Register Mapping ...................................... 162
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S
Selective Peripheral Module Control................................. 102 Serial Peripheral Interface (SPI) ....................................... 121 Setup for Continuous Output Pulse Generation................ 116 Setup for Single Output Pulse Generation ........................ 115 Software Simulator (MPLAB SIM)..................................... 209 Software Stack Pointer, Frame Pointer CALL Stack Frame...................................................... 42 Special Features ............................................................... 189 Code Protection ........................................................ 189 Flexible Configuration ............................................... 189 In-Circuit Emulation................................................... 189 In-Circuit Serial Programming (ICSP) ....................... 189 JTAG Boundary Scan Interface ................................ 189 Watchdog Timer (WDT) ............................................ 189 Special Function Register Reset States.............................. 57 Symbols Used in Opcode Descriptions............................. 200
U
UART Baud Rate Generator (BRG) .................................... 140 Infrared Support........................................................ 141 IrDA Built-in Encoder and Decoder........................... 141 External Support, Clock Output ........................ 141 Operation of UxCTS and UxRTS Control Pins ......... 141 Receiving 8-Bit or 9-Bit Data Mode ................................... 141 Transmitting 8-Bit Data Mode................................................ 141 9-Bit Data Mode................................................ 141 Break and Sync Sequence ............................... 141 Universal Asynchronous Receiver Transmitter (UART) ... 139
V
VDDCORE/VCAP Pin ........................................................... 195 Voltage Regulator (On-Chip) ............................................ 195
T
Timer1 Module .................................................................. 105 Timer2/3 Module ............................................................... 107 Timer4/5 Module ............................................................... 107 Timing Diagrams CLKO and I/O ........................................................... 222 External Clock ........................................................... 220 Timing Requirements Capacitive Loading on Output Pin ............................ 219 CLKO and I/O ........................................................... 222 External Clock ........................................................... 220 Timing Specifications PLL Clock.................................................................. 221
W
Watchdog Timer (WDT).................................................... 196 Control Register........................................................ 196 Programming Considerations ................................... 196 WWW Address ................................................................. 237 WWW, On-Line Support ....................................................... 8
DS39747E-page 236
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PIC24FJ128GA010 FAMILY
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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DS39747E-page 237
PIC24FJ128GA010 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39747E FAX: (______) _________ - _________
Device: PIC24FJ128GA010 Family Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39747E-page 238
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PIC24FJ128GA010 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 128 GA0 10 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern
b)
Examples:
a) PIC24FJ128GA008-I/PT 301: General purpose PIC24F, 96 KB program memory, 80-pin, Industrial temp., TQFP package, QTP pattern #301. PIC24FJ128GA010-I/PT: General purpose PIC24F, 128 KB program memory, 100-pin, Industrial temp., TQFP package.
Architecture Flash Memory Family Product Group Pin Count
24 FJ
= 16-bit modified Harvard without DSP = Flash program memory
GA0 = General purpose microcontrollers 06 08 10 I PT PF = 64-pin = 80-pin = 100-pin = -40C to +85C (Industrial) = 64-Lead, 80-Lead, 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
Temperature Range Package
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample
(c) 2009 Microchip Technology Inc.
DS39747E-page 239
WORLDWIDE SALES AND SERVICE
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03/26/09
DS39747E-page 240
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